An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS (集積回路)

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概要

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• An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.08 mm^2) by adopting 90 nm Si CMOS technology. In the proposed PLL, a phase-locked loop is implemented to ensure correct frequency locking. Final phase locking is done by injection locking to reduce phase noise. For a 300-MHz input reference signal, without injection locking, the 1-MHz-offset phase noise was -91.4 dBc/Hz (PLL output frequency: 7.2 GHz = 24×300 MHz); with injection locking, the noise was -107 dBc/Hz (spurious level: -32 dBc; power consumption from a 1.0 V power supply: 13.6 mW).

• 2011-12-08

著者

• ISHIHARA Noboru

  Solutions Research Laboratory, Tokyo Institute of Technology

• Masu K

  Research Institute Of Electrical Communication Tohoku University

• Masu Kazuya

  Integrated Research Institute

• Ito H

  National Agricultural Res. Organization Mie Jpn

• Ishihara Noboru

  東工大

• Masu Kazuya

  東工大

• Ito Hiroyuki

  Precision And Intelligence Laboratory Tokyo Institute Of Technology

• Itoh H

  Osaka Univ. Pharmaceutical Sci. Osaka Jpn

• Ito H

  Precision And Intelligence Laboratory Tokyo Institute Of Technology

• Masu Kazuya

  Solutions Research Laboratory Tokyo Institute Of Technology

• Ishihara Noboru

  Solutions Research Laboratory Tokyo Institute Of Technology

• Lee Sang_yeop

  Solutions Research Laboratory, Tokyo Institute of Technology

• Ito Hiroyuki

  Solutions Research Laboratory, Tokyo Institute of Technology

• Lee Sang_yeop

  Solutions Research Laboratory Tokyo Institute Of Technology

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