Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress

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概要

• 論文の詳細を見る

• A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90nm-and 65nm-CMOS technologies having the channel orientations of, respectively, ‹110› and ‹100›, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8mV for the threshold voltage, as opposed to ∼20% and ∼50mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

• （社）電子情報通信学会の論文
• 2008-07-01

著者

• Masu K

  Research Institute Of Electrical Communication Tohoku University

• Masu Kazuya

  Integrated Research Institute

• Masu Kazuya

  Tokyo Institute Of Technology

• Amakawa Shuhei

  Tokyo Inst. Of Technol. Yokohama‐shi Jpn

• Amakawa Shuhei

  Integrated Research Institute Tokyo Institute Of Technology

• YAMADA Kenta

  NEC Electronics Corporation

• SATO Takashi

  Tokyo Institute of Technology

• NAKAYAMA Noriaki

  Tokyo Institute of Technology

• KUMASHIRO Shigetaka

  MIRAI-Selete

• Tanoi Satoru

  東工大

• Masu Kazuya

  東工大

• Yamada Kenta

  Nec Electronics Corp. Kawasaki‐shi Jpn

• Masu Kazuya

  Tokyo Inst. Of Technol. Yokohama‐shi Jpn

• SATO Takashi

  Graduate School of Informatics, Kyoto University

• NAKAYAMA Noriaki

  Institute for Chemical Research,Kyoto University

• Nakayama Noriaki

  Semiconductor Technology Academic Research Center

• Sato Takashi

  Graduate School Of Informatics Kyoto University

• Masu Kazuya

  Solutions Research Laboratory Tokyo Institute Of Technology

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