On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement

スポンサーリンク

概要

• 論文の詳細を見る

• A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5- degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20MHz to 220MHz with 1MHz steps. The SFDR of 40dB is obtained at the noise frequency of 100MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.

• （社）電子情報通信学会の論文
• 2011-06-01

著者

• KUMASHIRO Shigetaka

  MIRAI-Selete

• Nagata Makoto

  Kobe Univ. Kobe‐shi Jpn

• Nagata Makoto

  Graduate School Of System Informatics Kobe University

• MOGAMI Tohru

  MIRAI-Selete

• Yamada Toshio

  Mirai-selete

• BANDO Yoji

  Graduate School of System Informatics, Kobe University

• TAKAYA Satoshi

  Graduate School of System Informatics, Kobe University

• OHKAWA Toru

  MIRAI-Selete

• TAKARAMOTO Toshiharu

  MIRAI-Selete

• Bando Yoji

  Graduate School Of System Informatics Kobe University

• Mogami Tohru

  Graduate School Of System Informatics Kobe University

• SODA Masaaki

  Dept. of Computer Science and System Engineering, Kobe University

• BANDO Yoji

  Dept. of Computer Science and System Engineering, Kobe University

• TAKAYA Satoshi

  Dept. of Computer Science and System Engineering, Kobe University

• NAGATA Makoto

  Dept. of Computer Science and System Engineering, Kobe University

• Mogami Tohru

  MIRAI--Selete, Tsukuba, Ibaraki 305-8569, Japan

関連論文

• A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System(Analog Circuits and Related SoC Integration Technologies)
• Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach(Novel Device Architectures and System Integration Technologies)
• Communication Scheme for a Highly Collision-Resistive RFID System( Analog Circuit Techniques and Related Topics)
• Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques(Special Section on Analog Circuit Techniques and Relate)
• A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation
• Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
• Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
• An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing(Special Issue on High-Performance Analog Integrated Circuits)
• Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies
• New Non-Volatile Analog Memory Circuits Using PWM Methods (Special Issue on Integrated Electronics and New System Paradigms)
• An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology
• Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
• Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
• Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements(Analog Circuits and Related SoC Integration Technologies)
• An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
• Channel Dopant Distribution in Metal--Oxide--Semiconductor Field-Effect Transistors Analyzed by Laser-Assisted Atom Probe Tomography
• Design of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance
• Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition(Logic Synthesis, VLSI Design and CAD Algorithms)
• Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, Low-Power LSI and Low-Power IP)
• Three-Dimensional Structure Analysis of Metal-Oxide-Insulator Field Effect Transistors with Different Electrical Properties by Scanning Transmission Electron Microscopy
• Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
• On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
• A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength
• On-Chip In-Place Measurements of V_ and Signal/Substrate Response of Differential Pair Transistors
• Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
• FOREWORD
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation
• Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits
• Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation (Special Issue : Solid State Devices and Materials)
• A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
• Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring

もっと見る 閉じる

スポンサーリンク