An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(<Special Section>Novel Device Architectures and System Integration Technologies)

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概要

• 論文の詳細を見る

• We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.

• 社団法人電子情報通信学会の論文
• 2006-11-01

著者

• Hirata Masaaki

  Matsushita Elect.

• Nagata Makoto

  Kobe Univ. Kobe‐shi Jpn

• Shimazaki Kenji

  Matsushita Elect.:kobe University

• FUKAZAWA Mitsuya

  Kobe University

• MIYAHARA Shingo

  Matsushita Elect.

• SATOH Kazuhiro

  Matsushita Elect.

• TSUJIKAWA Hiroyuki

  Matsushita Elect.

• Fukazawa Mitsuya

  Kobe Univ. Kobe‐shi Jpn

• Nagata Makoto

  Graduate School Of System Informatics Kobe University

• Nagata Makoto

  Kobe Univ.

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• FOREWORD
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation
• Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits
• Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation (Special Issue : Solid State Devices and Materials)
• A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
• Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring

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