Nagata Makoto | Graduate School Of System Informatics Kobe University

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概要

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著作論文

A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System(Analog Circuits and Related SoC Integration Technologies)
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach(Novel Device Architectures and System Integration Technologies)
Communication Scheme for a Highly Collision-Resistive RFID System( Analog Circuit Techniques and Related Topics)
Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques(Special Section on Analog Circuit Techniques and Relate)
A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation
Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing(Special Issue on High-Performance Analog Integrated Circuits)
Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies
New Non-Volatile Analog Memory Circuits Using PWM Methods (Special Issue on Integrated Electronics and New System Paradigms)
An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology
Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements(Analog Circuits and Related SoC Integration Technologies)
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
Design of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition(Logic Synthesis, VLSI Design and CAD Algorithms)
Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, Low-Power LSI and Low-Power IP)
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength
On-Chip In-Place Measurements of V_ and Signal/Substrate Response of Differential Pair Transistors
Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
FOREWORD
False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation
Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation (Special Issue : Solid State Devices and Materials)
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring

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