Nagata Makoto | Kobe Univ. Kobe‐shi Jpn

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概要

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著作論文

A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System(Analog Circuits and Related SoC Integration Technologies)
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach(Novel Device Architectures and System Integration Technologies)
Communication Scheme for a Highly Collision-Resistive RFID System( Analog Circuit Techniques and Related Topics)
Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements(Analog Circuits and Related SoC Integration Technologies)
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
Design of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition(Logic Synthesis, VLSI Design and CAD Algorithms)
Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, Low-Power LSI and Low-Power IP)
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias(Digital,Low-Power, High-Speed LSIs and Related Technologies)
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
On-Chip In-Place Measurements of V_ and Signal/Substrate Response of Differential Pair Transistors

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