Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, <Special Section>Low-Power LSI and Low-Power IP)

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概要

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• Dynamic power supply noise measurements with resolutions of 100ps and 100μV for 100ns and 1V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias network's AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• Hirano Shozo

  Matsushita Elect.

• Nagata Makoto

  Kobe Univ. Kobe‐shi Jpn

• Shimazaki Kenji

  Matsushita Elect.:kobe University

• TSUJIKAWA Hiroyuki

  Matsushita Elect.

• Nagata Makoto

  Graduate School Of System Informatics Kobe University

• OKUMOTO Takeshi

  Matsushita Electric Industrial Co. Ltd.

• Nagata Makoto

  Kobe Univ.

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• FOREWORD
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