Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques(<特集>Special Section on Analog Circuit Techniques and Relate)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes a new method for image segmentation and extraction using nonlinear cellular networks. Flexible segmentation of complicated natural scene images is achieved by using resistive-fuse networks, and each segmented regions is extracted by nonlinear oscillator networks. We also propose a nonlinear cellular network circuit implementing both resistive-fuse and oscillator dynamics by using pulse-modulation techniques. The basic operation of the nonlinear network circuit is confirmed by SPICE simulation. Moreover, the 10×10-pixel image segmentation and extraction are demonstrated by high-speed circuit simulation.

• 社団法人電子情報通信学会の論文
• 2002-02-01

著者

• Iwata Atsushi

  Graduate School Of Advanced Sciences Of Matter Hiroshima University

• NAGATA Makoto

  Department of Computer and Systems Engineering, Kobe University

• Iwata A

  Hiroshima Univ. Higashi-hiroshima‐shi Jpn

• NAGATA Makoto

  Graduate School of System Informatics, Kobe University

• Morie T

  Graduate School Of Life Science And Systems Engineering Kyushu Institute Of Technology

• Morie Takashi

  Graduate School Of Life Science And Systems Engineering Kyushu Institute Of Technology

• Miyake Makoto

  Matsushita Electric Industrial Co. Ltd.

• Miyake Makoto

  The Authors Are With Wireless Commun.department Information Technology R&d Center Mitsubishi Ele

• ANDO Hiroshi

  Graduate School of Engineering, Hiroshima University

• IWATA Atsushi

  A-R-Tec Corporation

• Iwata Atsushi

  Electronic Materials And Devices Division Mitsubishi Petrochemical Co. Ltd.

• Nagata M

  Department Of Computer And Systems Engineering Kobe University

• Nagata Makoto

  Graduate School Of System Informatics Kobe University

• Ando H

  Graduate School Of Engineering Hiroshima University

• Ando Hiroshi

  Graduate School Of Advanced Sciences Of Matter Hiroshima University

関連論文

• Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
• A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System(Analog Circuits and Related SoC Integration Technologies)
• Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach(Novel Device Architectures and System Integration Technologies)
• Communication Scheme for a Highly Collision-Resistive RFID System( Analog Circuit Techniques and Related Topics)
• MYOCARDIAL SYMPATHETIC ACTIVITY IN DOXORUBICIN (DOX)-INDUCED CARDIOTOXICITY IN RATS : RI : 53 Annual Scientific Meeting, Japanese Circulation Society
• PJ-065 Value of Late Gadolinium Enhancement by Magnetic Resonance in Patients with Cardiac Sarcoidosis : Characteristic Findings and Clinical Utility(PJ011,CT/MRI (Myocardium) 4 (I),Poster Session (Japanese),The 73rd Annual Scientific Meeting of The Japan
• -0043-EFFECTS OF METOPROLOL ON CARDIAC ADRENERGIC INNERVATION IN DOXORUBICIN (DOX)-INDUCED MYOCARDIAL DAMAGE IN RATS
• Immunohistochemical Localization of Endothelin in Cardiovascular Disease
• A Survivor-Correction Viterbi Algorithm
• An Adaptive List-Output Viterbi Equalizer with Fast Compare-Select Operation (Special Issue on Multimedia Mobile Communication Systems)
• -1089-DETEVTION OF MYOCARDIAL DAMAGE IN DOXORUBICIN CARDIOMYOPATHY OF RAT BY IN-111 ANTIMYOSIN ANTIBODY : THE 54th ANNUAL SCIENTIFIC MEETING OF THE JAPANESE CIRCULATION SOCIETY
• Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques(Special Section on Analog Circuit Techniques and Relate)
• A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation
• Image Object Extraction Using Resistive-Fuse and Oscillator Networks and a Pulse-Modulation Circuit for Their LSI Implementation
• A Current-Sampling-Mode CMOS Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach
• A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function
• An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture(Analog Circuit and Device Technologies)
• A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory(Novel Device Architectures and System Integration Technologies)
• Control of Electron Transport in Two-Dimensional Array of Si Nanodisks for Spiking Neuron Device
• Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
• High-Efficiency Micromirrors and Branched Optical Waveguides on Si Chips
• An Experimental Pattern Recognition System Using Bidirectional Optical Bus Lines
• Experimental Pattern Recognition System Using Bidirectional Optical Bus Lines
• Optically Interconnected Kohonen Net for Pattern Recognition
• Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps(New System Paradigms for Integrated Electronics)
• An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing(Special Issue on High-Performance Analog Integrated Circuits)
• A CMOS Stochastic Associative Processor Using PWM Chaotic Signals(Special Issue on Integrated Systems with New Concepts)
• Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies
• Merged Analog-Digital Circuits Using Pulse Modulation for Intellingent SoC Applications (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
• A High-Resolution Hadamard Transform Circuit Using Pulse Width Modulation Technique
• A Multi-Quantum-Dot Associative Circuit Using Thermal-Noise Assisted Tunneling
• A Nonlinear Oscillator Network for Gray-Level Image Segmentation and PWM / PPM Circuits for Its VLSI Implementation(Special Section on Intelligent Signal and Image Processing)
• New Non-Volatile Analog Memory Circuits Using PWM Methods (Special Issue on Integrated Electronics and New System Paradigms)
• A Stochastic Association Circuit Using PWM Chaotic Signals
• A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on Pulse Width Modulation
• An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique (Special Section on Analog Circuit Techniques and Related Topics)
• A Stochastic Associative Memory Using Single-Electron Devices and Its Application in Digit Pattern Association
• A Stochastic Associative Memory Using Single-Electron Tunneling Devices (Special Issue on Technology Challenges for Single Electron Devices)
• Model-Adaptable Parameter Extraction System for MOSFET Models
• Development of Module Generators from Extracted Design Procedures : Application to Analog Device Generation
• Analysis and Design of Low Loss and Low Mode-Shift Integrated Optical Waveguides Using Finite-Difference Time-Domain Method
• Resistivity Correction Factor for the Four-Ring Probe Method
• Resistivity Correction Factor for the Four-Probe Method: Experiment III
• Localization and Quantum Hall Effect in Two-Dimensional Systems Under Strong Magnetic Fields(Transport and Fermiology)
• Low-Voltage, Low-Phase-Noise Ring-VCO using 1/f-Noise Reduction Techniques
• A 0.6V Supply CMOS Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization
• Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
• A 1V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique(Analog Circuit and Device Technologies)
• Design of a Wireless Neural-Sensing LSI(Analog Circuit and Device Technologies)
• A Design of Neural Signal Sensing LSI with Multi-Input-Channels(Analog Circuit Techniques and Related Topics)
• Breakdown of the Quantum Hall Effect in GaAs/AlGaAs Heterostructures Due to Current
• A Neural Recording Amplifier with Low-Frequency Noise Suppression
• A 2.0Vpp Input, 0.5V Supply Delta Amplifier with A-to-D Conversion
• A Low Noise Amplifier Using Chopper Stabilization for a Neural Sensor LSI
• Peptide nucleic acid-locked nucleic acid polymerase chain reaction clamp-based detection test for gefitinib-refractory T790M epidermal growth factor receptor mutation
• Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications
• Ectopic activation of the transcription promoter for the testis-specific mouse Pgk-2 gene on elimination of a cis-acting upstream DNA region
• A stochastic computing chip for measurement of Manhattan distance
• Chip-Level Substrate Coupling Analysis with Reference Structures for Verification(Physical Design,VLSI Design and CAD Algorithms)
• Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits(Analog Circuit Techniques and Related Topics)
• An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology
• Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits
• On-Die Monitoring of Substrate Coupling for Mixed-Signal Circuit Isolation
• A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique(Optical, PLL, Analog Circuit and Device Technologies)
• A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique
• Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
• Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements(Analog Circuits and Related SoC Integration Technologies)
• An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
• Association of Tumor Necrosis Factor-α and Neutrophilic Inflammation in Severe Asthma
• Tulobuterol, a β2-agonist, Attenuates Eosinophil Adhesion to Endothelial Cells
• Design of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance
• Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices(Analog Circuits and Related SoC Integration Technologies)
• Electrical Activity of the Human Retina in Vitro(SYMPOSIUM ON ELECTRORETINOGRAPHY)
• Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition(Logic Synthesis, VLSI Design and CAD Algorithms)
• A High-Resolution CMOS Image Sensor with Hadamard Transform Function
• A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique
• Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, Low-Power LSI and Low-Power IP)
• Comparative and Histophysiological Study of Oil Droplets in the Avian Retina
• PCA-based Object Detection/Recognition Chip for Wireless Interconnected 3-D Integration
• Low-Voltage, Low-Phase-Noise Ring Voltage-Controlled Oscillator Using $1/ f$-Noise Reduction Techniques
• A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
• On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
• D-12-113 Particle Swarm Optimization for Template Matching
• A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength
• A Motion Detection Model Inspired by the Neuronal Propagation in the Hippocampus
• Analog CMOS circuit implementation of a pulse-coupled phase oscillator system and observation of synchronization phenomena
• On-Chip In-Place Measurements of V_ and Signal/Substrate Response of Differential Pair Transistors
• Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
• FOREWORD
• Principal Component Analysis-Based Object Detection/Recognition Chip for Wireless Interconnected Three-Dimensional Integration
• Stochastic Computing Chip for Measurement of Manhattan Distance
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation
• Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits
• 0.6 V Supply Complementary Metal Oxide Semiconductor Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization
• Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation (Special Issue : Solid State Devices and Materials)
• Evaluation of Digital Crosstalk Noise on Differential Input Voltage Controlled Oscillator
• A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
• Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring

もっと見る 閉じる

スポンサーリンク