A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation

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概要

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• Capacitor charging modeling accelerates the time-domain simulation of power current of cryptographic VLSI circuits in a CMOS technology. The model finely represents the amount of charges consumed during the operation of Advanced Encryption Standard (AES) cores in a variety of logical implementations, reflecting their internal logical activities. This approach significantly reduces the complexity of power current simulation, and accomplishes acceleration by a factor of more than 200 over the traditional transistor-level circuit simulation. The correlated power analysis (CPA) attack against AES cores is successfully simulated with a conventional circuit simulator, with the models individually derived for 10,000 different cipher texts. The CPA is also experimentally performed against AES cores fabricated in a 65nm as well as 130nm CMOS technologies, using SASEBO measurement standards. The fast power current simulation is demonstrated to be accurate enough to evaluate the vulnerability of AES cores in various logical implementations as well as in different technologies, and exhibits general agreements with the silicon measurements.

著者

• Sasaki Akihiko

  National Institute For Fusion Science

• Nagata Makoto

  Graduate School Of System Informatics Kobe University

• Fujimoto Daisuke

  Graduate School Of System Informatics Kobe University

• SASAKI Akihiko

  National Institute of Advanced Industrial Science and Technology

• KATASHITA Toshihiro

  National Institute of Advanced Industrial Science and Technology

• HORI Yohei

  National Institute of Advanced Industrial Science and Technology

• SATOH Akashi

  Graduate School of Infomatics and Engineering, The University of Electro-Communications

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