A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits

スポンサーリンク

概要

• 論文の詳細を見る

• A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with ±200mV at 2.5V, 1.0V, and 0.0V, respectively, with less than 4mV deviation among 240 probing channels.

• （社）電子情報通信学会の論文
• 2011-04-01

著者

• KUMASHIRO Shigetaka

  MIRAI-Selete

• Nagata Makoto

  Kobe Univ. Kobe‐shi Jpn

• Nagata Makoto

  Graduate School Of System Informatics Kobe University

• Yamada Toshio

  Mirai-selete

• Souda Masaaki

  Mirai-selete

• BANDO Yoji

  Graduate School of System Informatics, Kobe University

• TAKAYA Satoshi

  Graduate School of System Informatics, Kobe University

• OHKAWA Toru

  MIRAI-Selete

• TAKARAMOTO Toshiharu

  MIRAI-Selete

• MOGAMI Tohru

  Graduate School of System Informatics, Kobe University

• Bando Yoji

  Graduate School Of System Informatics Kobe University

• Takaya Satoshi

  Graduate School Of System Informatics Kobe University

• Mogami Tohru

  Graduate School Of System Informatics Kobe University

関連論文

• A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System(Analog Circuits and Related SoC Integration Technologies)
• Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach(Novel Device Architectures and System Integration Technologies)
• Communication Scheme for a Highly Collision-Resistive RFID System( Analog Circuit Techniques and Related Topics)
• Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques(Special Section on Analog Circuit Techniques and Relate)
• A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation
• Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
• Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
• An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing(Special Issue on High-Performance Analog Integrated Circuits)
• Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies
• New Non-Volatile Analog Memory Circuits Using PWM Methods (Special Issue on Integrated Electronics and New System Paradigms)
• An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology
• Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
• Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
• Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements(Analog Circuits and Related SoC Integration Technologies)
• An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
• Design of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance
• Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition(Logic Synthesis, VLSI Design and CAD Algorithms)
• Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, Low-Power LSI and Low-Power IP)
• Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
• On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
• A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength
• On-Chip In-Place Measurements of V_ and Signal/Substrate Response of Differential Pair Transistors
• Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
• FOREWORD
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation
• Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits
• Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation (Special Issue : Solid State Devices and Materials)
• A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
• Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring

もっと見る 閉じる

スポンサーリンク