Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns

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概要

• 論文の詳細を見る
• 2010-08-01

著者

• KUMASHIRO Shigetaka

  MIRAI-Selete

• Yoshimura Hisao

  Mirai-selete

• Yamada Kenta

  Mirai-selete

• SYO Toshiyuki

  MIRAI-Selete

• ITO Masaru

  MIRAI-Selete

• KUNIKIYO Tatsuya

  MIRAI-Selete

• KANAMOTO Toshiki

  MIRAI-Selete

関連論文

• Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
• Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
• A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
• On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
• On-Chip In-Place Measurements of V_ and Signal/Substrate Response of Differential Pair Transistors
• Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation

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