Communication Scheme for a Highly Collision-Resistive RFID System(<Special Section> Analog Circuit Techniques and Related Topics)

スポンサーリンク

概要

• 論文の詳細を見る

• A highly collision-resistive RFID system multiplexes communications between thousands of tags and a single reader in combination with time-domain multiplexing code division multiple access (TD-CDMA), CRC error detection, and re-transmission for error recovery. The collision probability due to a random selection of CDMA codes and TDMA channels bounds the number of IDs successfully transmitted to a reader during a limited time frame. However, theoretical analysis showed that the re-transmission greatly reduced the collision probability and that an ID error rate of 2.5×10^<-9> could be achieved when 1,000 ID tags responded within a time frame of 400 msec in ideal communication channels. The proposed collision-resistive communication scheme for a thousand multiplexed channels was modeled on a discrete-time digital expression and an FPGA-based emulator was built to evaluate a practical ID error rate under the presence of background noise in communication channels. To achieve simple anti-noise communication in a multiple-response RFID system, as well as unurged re-transmission of ID data, adjusting of correlator thresholds provides a significant improvement to the error rate. Thus, the proposed scheme does not require a reader to request ID transmission to erroneously responding tags. A reader also can lower noise influence by using correlator thresholds, since the scheme multiplexes IDs by CDMA-based communication. The effectiveness of the re-transmission was confirmed experimentally even in noisy channels, and the ID error rate derived from the emulation was 1.9×10^<-5>. The emulation was useful for deriving an optimum set of RFID system parameters to be used in the design of mixed analog and digital integrated circuits for RFID communication.

• 社団法人電子情報通信学会の論文
• 2006-02-01

著者

• Fukumizu Yohei

  Graduate School Of Science And Technology Kobe University

• Nagata Makoto

  the Department of Geriatrics, Tokyo Womens Medical University

• TAKI Kazuo

  AIL Co., Ltd.

• FUKUMIZU Yohei

  the Graduate School of Science and Technology, Kobe University

• OHNO Shuji

  the Graduate School of Science and Technology, Kobe University

• Ohno Shuji

  The Graduate School Of Science And Technology Kobe University

• Taki Kazuo

  Ail Co. Ltd.

• Nagata Makoto

  Kobe Univ. Kobe‐shi Jpn

• Nagata Makoto

  Graduate School Of System Informatics Kobe University

• Nagata Makoto

  the Department of Geriatrics, Tokyo Women's Medical University

関連論文

• Apoptotic Cell Death in Arrhythmogenic Right Ventricular Cardiomyopathy : A Comparative Study with Idiopathic Sustained Ventricular Tachycardia
• A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System(Analog Circuits and Related SoC Integration Technologies)
• Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach(Novel Device Architectures and System Integration Technologies)
• Communication Scheme for a Highly Collision-Resistive RFID System( Analog Circuit Techniques and Related Topics)
• Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques(Special Section on Analog Circuit Techniques and Relate)
• A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation
• Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
• An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing(Special Issue on High-Performance Analog Integrated Circuits)
• Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies
• New Non-Volatile Analog Memory Circuits Using PWM Methods (Special Issue on Integrated Electronics and New System Paradigms)
• An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology
• Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
• Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements(Analog Circuits and Related SoC Integration Technologies)
• An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
• Design of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance
• Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition(Logic Synthesis, VLSI Design and CAD Algorithms)
• Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, Low-Power LSI and Low-Power IP)
• Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias(Digital,Low-Power, High-Speed LSIs and Related Technologies)
• A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits
• On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement
• A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength
• On-Chip In-Place Measurements of V_ and Signal/Substrate Response of Differential Pair Transistors
• Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation
• Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
• FOREWORD
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation
• Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits
• Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation
• False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation (Special Issue : Solid State Devices and Materials)
• A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation
• Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring

もっと見る 閉じる

スポンサーリンク