Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits

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概要

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• Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).

著者

• Sasaki Yuta

  Graduate School Of Engineering Hokkaido University

• Nagata Makoto

  Graduate School Of System Informatics Kobe University

• Ichikawa Kouji

  Denso Corp. Kariya‐shi Jpn

• YOSHIKAWA Kumpei

  Graduate School of System Informatics, Kobe University

• SAITO Yoshiyuki

  Panasonic Corporation

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