Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits

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概要

• 論文の詳細を見る
• 2012-12-01

著者

• NAGATA Makoto

  the Graduate School of Advanced Sciences of Matter, Hiroshima University

• Ichikawa Kouji

  Denso Corp. Kariya‐shi Jpn

• SAITO Yoshiyuki

  Panasonic Corporation

• YOSHIKAWA Kumpei

  the Graduate School of System Informatics, Kobe University

• SASAKI Yuta

  the Graduate School of System Informatics, Kobe University

関連論文

• A CMOS Stochastic Associative Processor Using PWM Chaotic Signals(Special Issue on Integrated Systems with New Concepts)
• Merged Analog-Digital Circuits Using Pulse Modulation for Intellingent SoC Applications (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
• An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment
• Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
• Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits

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