Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits(<Special Section>Analog Circuit Techniques and Related Topics)
スポンサーリンク
概要
- 論文の詳細を見る
Substrate-coupling equivalent circuits can be derived for arbitrary isolation structures by F-matrix computation. The derived netlist represents a unified impedance network among multiple sites on a chip surface as well as internal nodes of isolation structures and can be applied with SPICE simulation to evaluate isolation strengths. Geometry dependency of isolation attributes to layout parameters such as area, width, and location distance. On the other hand, structural dependency arises from vertical impurity concentration specific to p^+/n^+ diffusion and deep n-well. Simulation-based prototyping of isolation structures can include all these dependences and strongly helps establish an isolation strategy against high-frequency substrate coupling in a given technology. The analysis of isolation strength provided by p^+/n^+ guard ring, deep n-well guard ring as well as deep n-well pocket well explains S21 measurements performed on high-frequency test structures targeting 5GHz bandwidth, that was formed in a 0.25-μm CMOS high frequency.
- 社団法人電子情報通信学会の論文
- 2007-02-01
著者
-
Iwata Atsushi
Graduate School Of Advanced Sciences Of Matter Hiroshima University
-
NAGATA Makoto
Department of Computer and Systems Engineering, Kobe University
-
MURASAKA Yoshitaka
A-R-Tec Corp.
-
Iwata A
Hiroshima Univ. Higashi-hiroshima‐shi Jpn
-
NAGATA Makoto
Graduate School of System Informatics, Kobe University
-
IWATA Atsushi
A-R-Tec Corporation
-
Murasaka Yoshitaka
A-r-tec Corporation
-
KOSAKA Daisuke
Department of Computer and Systems Engineering, Kobe University
-
Kosaka Daisuke
A-r-tec Corporation
-
Kosaka Daisuke
Department Of Computer And Systems Engineering Kobe University
-
Nagata Makoto
Department Of Computer And Systems Engineering Kobe University
-
Nagata Makoto
Department Of Computer And Systems Engineering Kobe University:a-r-tec Corporation
-
Iwata Atsushi
A-r-tec Corp.
関連論文
- Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
- Ehlers-Danlos Syndrome Type IV, Vascular Type, Which Demonstrated a Novel Point Mutation in the COL3A1 Gene
- A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System(Analog Circuits and Related SoC Integration Technologies)
- Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach(Novel Device Architectures and System Integration Technologies)
- Evaluation of Digital Crosstalk Noise on a Differential Input VCO
- MYOCARDIAL SYMPATHETIC ACTIVITY IN DOXORUBICIN (DOX)-INDUCED CARDIOTOXICITY IN RATS : RI : 53 Annual Scientific Meeting, Japanese Circulation Society
- PJ-065 Value of Late Gadolinium Enhancement by Magnetic Resonance in Patients with Cardiac Sarcoidosis : Characteristic Findings and Clinical Utility(PJ011,CT/MRI (Myocardium) 4 (I),Poster Session (Japanese),The 73rd Annual Scientific Meeting of The Japan
- -0043-EFFECTS OF METOPROLOL ON CARDIAC ADRENERGIC INNERVATION IN DOXORUBICIN (DOX)-INDUCED MYOCARDIAL DAMAGE IN RATS
- Immunohistochemical Localization of Endothelin in Cardiovascular Disease
- -1089-DETEVTION OF MYOCARDIAL DAMAGE IN DOXORUBICIN CARDIOMYOPATHY OF RAT BY IN-111 ANTIMYOSIN ANTIBODY : THE 54th ANNUAL SCIENTIFIC MEETING OF THE JAPANESE CIRCULATION SOCIETY
- Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques(Special Section on Analog Circuit Techniques and Relate)
- A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation
- Image Object Extraction Using Resistive-Fuse and Oscillator Networks and a Pulse-Modulation Circuit for Their LSI Implementation
- An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture(Analog Circuit and Device Technologies)
- A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory(Novel Device Architectures and System Integration Technologies)
- High-Efficiency Micromirrors and Branched Optical Waveguides on Si Chips
- An Experimental Pattern Recognition System Using Bidirectional Optical Bus Lines
- Experimental Pattern Recognition System Using Bidirectional Optical Bus Lines
- Optically Interconnected Kohonen Net for Pattern Recognition
- Pulse Modulation Techniques for Nonlinear Dynamical Systems and a CMOS Chaos Circuit with Arbitrary 1-D Maps(New System Paradigms for Integrated Electronics)
- An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing(Special Issue on High-Performance Analog Integrated Circuits)
- A CMOS Stochastic Associative Processor Using PWM Chaotic Signals(Special Issue on Integrated Systems with New Concepts)
- Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies
- Merged Analog-Digital Circuits Using Pulse Modulation for Intellingent SoC Applications (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
- A High-Resolution Hadamard Transform Circuit Using Pulse Width Modulation Technique
- A Multi-Quantum-Dot Associative Circuit Using Thermal-Noise Assisted Tunneling
- A Nonlinear Oscillator Network for Gray-Level Image Segmentation and PWM / PPM Circuits for Its VLSI Implementation(Special Section on Intelligent Signal and Image Processing)
- New Non-Volatile Analog Memory Circuits Using PWM Methods (Special Issue on Integrated Electronics and New System Paradigms)
- A Stochastic Association Circuit Using PWM Chaotic Signals
- A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on Pulse Width Modulation
- An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique (Special Section on Analog Circuit Techniques and Related Topics)
- A Stochastic Associative Memory Using Single-Electron Devices and Its Application in Digit Pattern Association
- A Stochastic Associative Memory Using Single-Electron Tunneling Devices (Special Issue on Technology Challenges for Single Electron Devices)
- Analysis and Design of Low Loss and Low Mode-Shift Integrated Optical Waveguides Using Finite-Difference Time-Domain Method
- Resistivity Correction Factor for the Four-Ring Probe Method
- Resistivity Correction Factor for the Four-Probe Method: Experiment III
- Localization and Quantum Hall Effect in Two-Dimensional Systems Under Strong Magnetic Fields(Transport and Fermiology)
- Low-Voltage, Low-Phase-Noise Ring-VCO using 1/f-Noise Reduction Techniques
- A 0.6V Supply CMOS Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization
- Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
- A 1V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique(Analog Circuit and Device Technologies)
- Design of a Wireless Neural-Sensing LSI(Analog Circuit and Device Technologies)
- A Design of Neural Signal Sensing LSI with Multi-Input-Channels(Analog Circuit Techniques and Related Topics)
- Breakdown of the Quantum Hall Effect in GaAs/AlGaAs Heterostructures Due to Current
- A Neural Recording Amplifier with Low-Frequency Noise Suppression
- A 2.0Vpp Input, 0.5V Supply Delta Amplifier with A-to-D Conversion
- A Low Noise Amplifier Using Chopper Stabilization for a Neural Sensor LSI
- Peptide nucleic acid-locked nucleic acid polymerase chain reaction clamp-based detection test for gefitinib-refractory T790M epidermal growth factor receptor mutation
- Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications
- A stochastic computing chip for measurement of Manhattan distance
- Chip-Level Substrate Coupling Analysis with Reference Structures for Verification(Physical Design,VLSI Design and CAD Algorithms)
- Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits(Analog Circuit Techniques and Related Topics)
- An Arbitrary Digital Power Noise Generator Using 65nm CMOS Technology
- Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits
- On-Die Monitoring of Substrate Coupling for Mixed-Signal Circuit Isolation
- A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique(Optical, PLL, Analog Circuit and Device Technologies)
- A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique
- A High-Linearity Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems
- Association of Tumor Necrosis Factor-α and Neutrophilic Inflammation in Severe Asthma
- Tulobuterol, a β2-agonist, Attenuates Eosinophil Adhesion to Endothelial Cells
- Design of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance
- Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices(Analog Circuits and Related SoC Integration Technologies)
- Electrical Activity of the Human Retina in Vitro(SYMPOSIUM ON ELECTRORETINOGRAPHY)
- Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition(Logic Synthesis, VLSI Design and CAD Algorithms)
- A High-Resolution CMOS Image Sensor with Hadamard Transform Function
- A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique
- PCA-based Object Detection/Recognition Chip for Wireless Interconnected 3-D Integration
- Low-Voltage, Low-Phase-Noise Ring Voltage-Controlled Oscillator Using $1/ f$-Noise Reduction Techniques
- Background Calibration Techniques for Low-Power and High-Speed Data Conversion
- On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration(Analog Circuits and Related SoC Integration Technologies)
- An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity(Analog Circuit and Device Technologies)
- Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise(Novel Device Architectures and System Integration Technologies)
- Allergen Immunotherapy in Asthma : Current Status and Future Perspectives
- Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs
- Differential effects of corticosteroids and theophylline on the adhesive interaction between eosinophils and endothelial cells
- FOREWORD
- On-Die Monitoring of Substrate Coupling for Mixed-Signal Circuit Isolation
- Stochastic Computing Chip for Measurement of Manhattan Distance
- Reference Complementary Metal–Oxide–Semiconductor Circuits and Test Structures for Evaluation of Dynamic Noise in Power Delivery Networks
- 0.6 V Supply Complementary Metal Oxide Semiconductor Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization
- Evaluation of Digital Crosstalk Noise on Differential Input Voltage Controlled Oscillator
- High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition(Electronic Circuits)