0.6 V Supply Complementary Metal Oxide Semiconductor Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization
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概要
- 論文の詳細を見る
Increasing dc offset voltage and $1/ f$ noise becomes a serious problem in scaled complementary metal oxide semiconductor (CMOS) technologies. In particular, device deviation causes a large dc offset voltage in an amplifier, and the circuit design with a low-power supply voltage becomes difficult. In this paper, a noise reduction technique and calibration techniques for device deviation with a low supply voltage are presented. The proposed techniques achieve autozeroing and chopper stabilization without using analog switches. The low-noise amplifier fabricated by 0.18 um CMOS technology was measured with a 0.6 V supply, and achieved 130 μW power consumption, 89 nV/$\sqrt{\text{Hz}}$ input noise (at 100 Hz).
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-04-30
著者
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Iwata Atsushi
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Sasaki Mamoru
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Yoshida Takeshi
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Masui Yoshihiro
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Masui Yoshihiro
Graduate School of Advanced Sciences of Matter, Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan
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Iwata Atsushi
Graduate School of Advanced Sciences of Matter, Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan
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Sasaki Mamoru
Graduate School of Advanced Sciences of Matter, Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan
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