A 2V 250 MHz VLIW Multimedia Processor(Special Issue on Multimedia, Network, and DRAM LSIs)
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概要
- 論文の詳細を見る
A dual-issue VLIW processor, running at 250MHz, is enhanced with multimedia instructions for a sustained peak performance of 1000MOPS. The multimedia processor integrates 300K transistors in an 8mm^2 core area and it is fabricated onto a 6mm×6.2mm chip with 32kB instruction and 32kB data RAMs in a 0.3-micrometer, four-layer metal CMOS process. It consumes 1.2W at 2.0V running at 250MHz. The VLIW processor achieves a speed-up of more than 4 times over a single-issue RISC for MPEG video block decoding. A decoder implemented on the multimedia processor with a small amount of dedicated hardware, such as the Huffman decoder and a DMA controller will decode the worst case 8×8 video block data in 754 cycles, leading to a real-time MPEG-2 system, video, and audio decoding system.
- 社団法人電子情報通信学会の論文
- 1998-05-25
著者
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TAKATA Hidehiro
Renesas Technology
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Yoshida Takeshi
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Yoshida T
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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SHIMAZU Yukihiko
Mitsubishi Electric Corporation
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TAKATA Hidehiro
Mitsubishi Electric Corporation
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Mohri Atsushi
Mitsubishi Electric Corporation
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Yamada A
Wireless Laboratories Ntt Docomo Inc.
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Holmann Edgar
Mitsubishi Electric Corporation
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YOSHIDA Toyohiko
Mitsubishi Electric Corporation
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YAMADA Akira
Mitsubishi Electric Corporation
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NAKAKIMURA Kiyoshi
Mitsubishi Electric Corporation
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HIGASHITANI Keiichi
Mitsubishi Electric Corporation
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