Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
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概要
- 論文の詳細を見る
Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
- 2009-04-01
著者
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NAGATA Makoto
Department of Computer and Systems Engineering, Kobe University
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TAKATA Hidehiro
Renesas Technology
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AKIYAMA Rei
Renesas Device Design
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Kurimoto Masanori
Renesas Technology Corporation
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Akiyama Rei
Renesas Design Corporation
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Takata Hidehiro
Renesas Technol. Corp. Itami‐shi Jpn
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Takata Hidehiro
Renesas Technology Corporation
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FUKAZAWA Mitsuya
Department of Computer Science and Systems Engineering, Graduate School of Engineering, Kobe Univers
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Fukazawa Mitsuya
Department Of Computer Science And Systems Engineering Graduate School Of Engineering Kobe Universit
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Nagata Makoto
Department Of Computer Science And Systems Engineering Graduate School Of Engineering Kobe Universit
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Nagata Makoto
Department Of Computer And Systems Engineering Kobe University
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Takata Hidehiro
Renesas Electronics Corporation
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