An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity(<Special Section>Analog Circuit and Device Technologies)
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概要
- 論文の詳細を見る
A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device geometry, followed by a current-mode sample and a hold circuit that is connected to a shared current output bus. A prototype signal monitor circuit demonstrated a 1.1-GHz effective bandwidth for 1.0-V full-swing digital signals in a 90-nm CMOS technology, where the monitor used 2.5-V I/O CMOS transistors and occupied a 30μm×120μm silicon area. We also showed that such signal monitor circuits can be tailored to sense of power-supply, ground, as well as full-swing logic signal wirings, and form an array with a single current output. Therefore, an on-chip multi-channel signal monitor enables multiple-points as well as multiple-voltage domain waveform acquisition for the purpose of the in-depth study of digital signal integrity.
- 一般社団法人電子情報通信学会の論文
- 2006-06-01
著者
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Nagata Makoto
Department Of Computer And Systems Engineering Kobe University
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NOGUCHI Koichiro
Graduate School of Science and Technology, Kobe University
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Noguchi Koichiro
Kobe Univ. Kobe‐shi Jpn
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Noguchi Koichiro
Graduate School Of Science And Technology Kobe University
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