Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits
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概要
- 論文の詳細を見る
Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.
- （社）電子情報通信学会の論文
- 2010-02-01
著者
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NAGATA Makoto
Department of Computer and Systems Engineering, Kobe University
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NAGATA Makoto
Graduate School of System Informatics, Kobe University
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Matsuno Tetsuro
Graduate School Of System Informatics Kobe University
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KOSAKA Daisuke
Department of Computer and Systems Engineering, Kobe University
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Kosaka Daisuke
A-r-tec Corporation
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MATSUNO Tetsuro
Department of Computer and Systems Engineering, Kobe University
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Kosaka Daisuke
Department Of Computer And Systems Engineering Kobe University
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Nagata Makoto
Department Of Computer And Systems Engineering Kobe University
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Nagata Makoto
Department Of Computer And Systems Engineering Kobe University:a-r-tec Corporation
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