Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices(<Special Section>Analog Circuits and Related SoC Integration Technologies)
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概要
- 論文の詳細を見る
Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-μm CMOS was measured at a 0.6-V supply, and achieved 89-nV/√<Hz> input referred noise (at 100Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68dBc/Hz at 100-kHz offset, 710-μW power dissipation at 1-V power supply.
- 社団法人電子情報通信学会の論文
- 2007-06-01
著者
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Iwata Atsushi
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Iwata A
Hiroshima Univ. Higashi-hiroshima‐shi Jpn
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Sasaki Mamoru
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Sasaki Mamoru
Hiroshima Univ. Higashihiroshima‐shi Jpn
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YOSHIDA Takeshi
Graduate School of Human and Environmental Studies, Kyoto University
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Yoshida Takeshi
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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Iwata Atsushi
Electronic Materials And Devices Division Mitsubishi Petrochemical Co. Ltd.
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Yoshida T
Graduate School Of Advanced Sciences Of Matter Hiroshima University
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SHIOZAKI Mitsuru
Graduate School of Advanced Sciences of Matter, Hiroshima University
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Iwata Atsushi
Nec Corp. Kawasaki‐shi Jpn
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