A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation(Parasitics and Noise)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• Large-scale integration (LSI) microchips are widely used in many types of modern electronic products including electric appliances, cellular phones, toys, electronic games, and automobiles. The electromagnetic interference (EMI) noise produced by these micro devices can cause significant operational problems in other devices in the system. Some methods that have been proposed for such analysis estimates the EMI noise characteristic through transistor-level power simulation. However, in these methods, transistor-level circuit simulation is performed by combining the power-supply impedance model and the power-supply source model. In general, transistor-level simulators are too slow for practical application-specific integrated circuit (ASIC) design. In this paper, a total solution for reducing EMI noise in LSI microchips was presented. The proposed design methodology integrates fast and accurate estimation, reduction, and verification. The method was successfully applied to the design of a 32-bit microprocessor, achieving a 2-dB noise reduction in the FM frequency band and 10-dB reduction at 1GHz. The proposed design methodology is a powerful solution for LSI designers as a tool for minimizing EMI noise and achieve higher levels of reliability for the microelectronic products.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• Hirano Shozo

  Matsushita Elect.

• Shimazaki Kenji

  Matsushita Elect.:kobe University

• TSUJIKAWA Hiroyuki

  Matsushita Elect.

• TSUJIKAWA Hiroyuki

  System LSI Technology Development Center, Semiconductor Company, Matsushita Electric Industrial Co.,

• HIRANO Shozo

  System LSI Technology Development Center, Semiconductor Company, Matsushita Electric Industrial Co.,

• SHIMAZAKI Kenji

  System LSI Technology Development Center, Semiconductor Company, Matsushita Electric Industrial Co.,

関連論文

• An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
• Power-Supply Noise Reduction with Design for Manufacturability(Power/Ground Network, VLSI Design and CAD Algorithms)
• Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, Low-Power LSI and Low-Power IP)
• A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation(Parasitics and Noise)(VLSI Design and CAD Algorithms)

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