Power-Supply Noise Reduction with Design for Manufacturability(Power/Ground Network, <Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).

• 社団法人電子情報通信学会の論文
• 2005-12-01

著者

• Hirano Shozo

  Matsushita Elect.

• Shimazaki Kenji

  Matsushita Elect.:kobe University

• Hirofuji Masanori

  Matsushita Elect.

• Sato Kazuhiro

  Matsushita Elect.

• TSUJIKAWA Hiroyuki

  Matsushita Elect.

• Shimada Junichi

  Matsushita Elect.

• ITO Mitsumi

  Matsushita Elect.

• MUKAI Kiyohito

  Matsushita Elect.

関連論文

• An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
• Power-Supply Noise Reduction with Design for Manufacturability(Power/Ground Network, VLSI Design and CAD Algorithms)
• Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits(Digital, Low-Power LSI and Low-Power IP)
• A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation(Parasitics and Noise)(VLSI Design and CAD Algorithms)

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