YAMADA Kenta | NEC Electronics Corporation
スポンサーリンク
概要
関連著者
-
YAMADA Kenta
NEC Electronics Corporation
-
Yamada Kenta
Nec Electronics Corp. Kawasaki‐shi Jpn
-
Oda Noriaki
Nec Electronics Corp. Kawasaki‐shi Jpn
-
Suzuki Mieko
Nec Electronics Corporation
-
Yamanaga Koh
Integrated Research Institute Tokyo Institute Of Technology
-
Sekine Makoto
Nec Electronics Corporation
-
Oda Noriaki
Ulsi Device Development Division Nec Corporation
-
Kunishima Hiroyuki
Nec Electronics Corporation
-
Takewaki Toshiyuki
Nec Electronics Corporation
-
UENO Kazuyoshi
NEC Electronics Corporation
-
OHNISHI Sadayuki
NEC Electronics Corporation
-
Honma Ichiro
Nec Electronics Corp. Kanagawa Jpn
-
林 喜宏
NECシステムデバイス研究所
-
林 喜宏
日本電気株式会社デバイスプラットフォーム研究所
-
林 喜宏
日本電気株式会社マイクロエレクトロニクス研究所 超高集積回路研究部
-
Masu K
Research Institute Of Electrical Communication Tohoku University
-
Masu Kazuya
Integrated Research Institute
-
Masu Kazuya
Tokyo Institute Of Technology
-
Goto Takayuki
Nec Electronics Corporation
-
OHTO Koichi
NEC Electronics
-
Hayashi Yoshihiro
Nec Corp. Kanagawa Jpn
-
Amakawa Shuhei
Tokyo Inst. Of Technol. Yokohama‐shi Jpn
-
Amakawa Shuhei
Integrated Research Institute Tokyo Institute Of Technology
-
SATO Takashi
Tokyo Institute of Technology
-
NAKAYAMA Noriaki
Tokyo Institute of Technology
-
KUMASHIRO Shigetaka
MIRAI-Selete
-
Tanoi Satoru
東工大
-
Masu Kazuya
東工大
-
Masu Kazuya
Tokyo Inst. Of Technol. Yokohama‐shi Jpn
-
SATO Takashi
Graduate School of Informatics, Kyoto University
-
NAKAYAMA Noriaki
Institute for Chemical Research,Kyoto University
-
HAYASHI Yoshihiro
Device Platforms Research Labs., NEC.
-
Nakayama Noriaki
Semiconductor Technology Academic Research Center
-
Horiuchi Tadahiko
Nec Electronics Corporation
-
Iguchi Manabu
Nec Electronics Corporation
-
Ikeda Masahiro
Nec Electronics Corporation
-
ITO Shinya
NEC Electronics Corporation
-
SHIBA Kazutoshi
NEC Electronics Corporation
-
HIRONAGA Nobuo
NEC Electronics Corporation
-
HONMA Ichiro
NEC Electronics Corporation
-
NANBA Hiroaki
NEC Electronics Corporation
-
YOKOGAWA Shinji
NEC Electronics Corporation
-
KAMEYAMA Akiko
NEC Electronics Corporation
-
USAMI Tatsuya
NEC Electronics Corporation
-
KUBO Akira
NEC Electronics Corporation
-
YAMAMOTO Yoshiaki
NEC Electronics Corporation
-
WATANABE Susumu
NEC Electronics Corporation
-
Sone Shuji
Nec Electronics Corporation
-
Ohto Koichi
Nec Electronics Corporation
-
Sakamoto Hideo
Nec Electronics Corporation
-
KITAHARA Hiroshi
NEC Electronics Corporation
-
ASAI Yoshihiko
NEC Electronics Corporation
-
OKADA Norio
NEC Electronics Corporation
-
YASUDA Makoto
NEC Electronics Corporation
-
SAKURAI Michio
NEC Electronics Corporation
-
HIROI Masayuki
NEC Electronics Corporation
-
MINDA Hiroyasu
NEC Electronics Corporation
-
Sato Takashi
Graduate School Of Informatics Kyoto University
-
Oda Noriaki
Nec Electronics Corporation
-
Yasuda Makoto
Nec Electronics Corp. Kawasaki‐shi Jpn
-
Shiba K
Nec Electronics Corporation
-
Shiba Kazutoshi
Ulsi Device Development Division Nec Corporation
-
IMURA Hironori
NEC Electronics Corporation
-
KAWAHARA Naoyoshi
NEC Electronics Corporation
-
TAGAMI Masayoshi
NEC Electronics Corporation
-
KAKUHARA Yumi
NEC Electronics Corporation
-
Kitahara Hiroshi
Nec Electronics Corp. Kawasaki‐shi Jpn
-
Masu Kazuya
Solutions Research Laboratory Tokyo Institute Of Technology
-
Hayashi Yoshihiro
Nec Corporation
-
Hayashi Yoshihiro
LSI Fundamental Research Laboratory, NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
-
Hayashi Yoshihiro
System Devices Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
-
Hayashi Yoshihiro
System Devices Research Laboratories, NEC, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
-
Hayashi Yoshihiro
System Devices and Fundamental Research, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
-
Hayashi Yoshihiro
Microelectronics Research Laboratories, NEC, 1120, Shimokuzawa, Sagamihara, Kanagawa 229, Japan
著作論文
- Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
- Accurate Modeling Method for Cu Interconnect
- Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)
- A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13μm Complementary Metal Oxide Semiconductor Generation
- Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45nm CMOS Generation(Device,Low-Power, High-Speed LSIs and Related Technologies)