Oda Noriaki | Nec Electronics Corp. Kawasaki‐shi Jpn

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著作論文

Accurate Modeling Method for Cu Interconnect
Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)
A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13μm Complementary Metal Oxide Semiconductor Generation
Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13μm CMOS Generation and Beyond(Novel Device Architectures and System Integration Technologies)
Dual Damascene Interconnect Technology for 130-nm-node Complementary Metal-Oxide-Semiconductor Devices Using Ladder-Oxide Film
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45nm CMOS Generation(Device,Low-Power, High-Speed LSIs and Related Technologies)
Key mechanisms for improved EM lifetime of CoWP capped Cu interconnects

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