Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13μm CMOS Generation and Beyond(<Special Section>Novel Device Architectures and System Integration Technologies)
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概要
- 論文の詳細を見る
A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13μm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.
- 社団法人電子情報通信学会の論文
- 2006-11-01
著者
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Oda Noriaki
Nec Electronics Corp. Kawasaki‐shi Jpn
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Kunishima Hiroyuki
Nec Electronics Corporation
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Takewaki Toshiyuki
Nec Electronics Corporation
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Ikeda Masahiro
Nec Electronics Corporation
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KYOUNO Takashi
NEC Electronics Corporation
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TAKEDA Kazuhiro
NEC Electronics Corporation
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TANAKA Tomoaki
NEC Electronics Corporation
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Oda Noriaki
Ulsi Device Development Division Nec Corporation
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