KAKUHARA Yumi | NEC Electronics Corporation

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概要

• KAKUHARA Yumiの詳細を見る
• 同名の論文著者
• NEC Electronics Corporationの論文著者

関連著者

• Oda Noriaki

  Nec Electronics Corp. Kawasaki‐shi Jpn

• UENO Kazuyoshi

  NEC Electronics Corporation

• KAWAHARA Naoyoshi

  NEC Electronics Corporation

• KAKUHARA Yumi

  NEC Electronics Corporation

• Oda Noriaki

  Ulsi Device Development Division Nec Corporation

• 林 喜宏

  NECシステムデバイス研究所

• 林 喜宏

  日本電気株式会社デバイスプラットフォーム研究所

• 林 喜宏

  日本電気株式会社マイクロエレクトロニクス研究所 超高集積回路研究部

• Hayashi Yoshihiro

  Nec Corp. Kanagawa Jpn

• YAMADA Kenta

  NEC Electronics Corporation

• Yamada Kenta

  Nec Electronics Corp. Kawasaki‐shi Jpn

• HAYASHI Yoshihiro

  Device Platforms Research Labs., NEC.

• Kunishima Hiroyuki

  Nec Electronics Corporation

• Suzuki Mieko

  Nec Electronics Corporation

• Sone Shuji

  Nec Electronics Corporation

• Yamanaga Koh

  Integrated Research Institute Tokyo Institute Of Technology

• Sekine Makoto

  Nec Electronics Corporation

• OHNISHI Sadayuki

  NEC Electronics Corporation

• IMURA Hironori

  NEC Electronics Corporation

• TAGAMI Masayoshi

  NEC Electronics Corporation

• Honma Ichiro

  Nec Electronics Corp. Kanagawa Jpn

• UENO Kazuyoshi

  Shibaura Institute of Technology, Dept. of Electronic Engineering

• Hayashi Yoshihiro

  Nec Corporation

• Hayashi Yoshihiro

  LSI Fundamental Research Laboratory, NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan

• Hayashi Yoshihiro

  System Devices Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan

• Hayashi Yoshihiro

  System Devices Research Laboratories, NEC, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan

• Hayashi Yoshihiro

  System Devices and Fundamental Research, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan

• Hayashi Yoshihiro

  Microelectronics Research Laboratories, NEC, 1120, Shimokuzawa, Sagamihara, Kanagawa 229, Japan

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著作論文

• Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45nm CMOS Generation(Device,Low-Power, High-Speed LSIs and Related Technologies)
• Key mechanisms for improved EM lifetime of CoWP capped Cu interconnects

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