Design of On-Chip High Speed Interconnect on Complementary Metal Oxide Semiconductor 180 nm Technology
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概要
- 論文の詳細を見る
Equalization is the technology to improve the performance of the on-chip or input/output (I/O) serial link, and the finite/infinite impulse response (FIR/IIR) filter based design is often used as an approximation to the analog filter for equalization, due to the ease of implementation with complementary metal oxide semiconductor (CMOS) technology. However, it has a significant challenge on this application with the analytical approach to the design parameter optimization, due to the severe non-linearity of the circuit. This paper shows how the analytical approach can be achieved to the very simple equalizer application. The analytical model was built and the parameter optimization method was proposed. The model was compared with the actual circuit, and the validity and the limitation of the model were discussed. The test structure was manufactured to prove the method, while the direction was identified on how the model should be improved to extend the analytical approach to this application.
- 2010-04-25
著者
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Amakawa Shuhei
Integrated Research Institute Tokyo Institute Of Technology
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Shuhei Amakawa
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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Ishihara Noboru
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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Kazuya Masu
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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Oshita Takao
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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Takao Oshita
Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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Ishihara Noboru
Integrated Research Institute, Tokyo Institute of Technology
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