A Compact Model of the Pinch-off Region of 100nm MOSFETs Based on the Surface-Potential(Semiconductor Materials and Devices)

スポンサーリンク

概要

• 論文の詳細を見る

• We have developed a model for circuit-simulation which describes the MOSFET region from pinch-off to drain contact based on the surface potential. The model relates the surface-potential increase beyond the pinch-off point to the channel/drain junction profile by applying the Gauss law with the assumption that the lateral field is greater than the vertical one. Explicit equations for the lateral field and the pinch-off length are obtained, which take the potential increase in the drain overlap region into account. The model, as implemented into a circuit simulator, correctly reproduces measured channel conductance and overlap capacitance for 100nm pocket-implant technologies as a function of bias condition and gate length.

• 社団法人電子情報通信学会の論文
• 2005-05-01

著者

• NAKAYAMA Noriaki

  Semiconductor Technology Academic Research Center(STARC)

• Mattausch Hans

  Hiroshima Univ. Higashihiroshima‐shi Jpn

• Mattausch Hans

  Research Center For Nanodevices And Systems Hiroshima University

• Ueno Hiroki

  Department Of Electrical And Electronic Engineering Chuo University

• NAKAYAMA Noriaki

  Tokyo Institute of Technology

• Mattausch Hans

  Hiroshima University

• Kumashiro Shigetaka

  Semiconductor Technology Academic Research Center

• Kumashiro S

  Ulsi Device Development Division Nec Corporation

• NAKAYAMA Noriaki

  Institute for Chemical Research,Kyoto University

• Nakayama Noriaki

  Semiconductor Technology Academic Research Center

• Mattausch Hans

  Research Institute For Nanodevice And Bio Systems Hiroshima University

• Navarro Dondee

  Graduate School Of Advanced Sciences Of Matter Hiroshima University

• Ueno H

  Graduate School Of Advanced Sciences Of Matter Hiroshima University:(present Address)matsushita Semi

• Ueno Hiroaki

  Graduate School Of Advanced Sciences Of Matter Hiroshima University

• Mizoguchi Takeshi

  Semiconductor Technology Academic Research Center

• HISAMITSU Kazuya

  Graduate School of Advanced Sciences of Matter,Hiroshima University

• YAMAGUCHI Tetsuya

  Semiconductor Technology Academic Research Center

• YAMASHITA Kyoji

  Semiconductor Technology Academic Research Center

• MIZOGUCHI Takeshi

  Graduate School of Advanced Sciences of Matter, Hiroshima University

• SUETAKE Masami

  Graduate School of Advanced Sciences of Matter, Hiroshima University

• MATTAUSCH Mitiko

  Graduate School of Advanced Sciences of Matter, Hiroshima University

• Suetake Masami

  Graduate School Of Advanced Sciences Of Matter Hiroshima University:(present Address)jfe Steel Corpo

• Miura‐mattausch M

  Hiroshima Univ. Higashi‐hiroshima Jpn

• Nakayama N

  Department Of Advanced Materials Science And Engineering Faculty Of Engineering Yamaguchi University

• Hisamitsu Kazuya

  Graduate School Of Advanced Sciences Of Matter Hiroshima University:(present Address)fujitsu Laborat

• Miura-mattausch Mitiko

  Hiroshima-university

• NAVARRO Dondee

  Graduate School of Advanced Sciences of Matter, Hiroshima University

関連論文

• Influence of Thermal Noise on Drain Current in Very Small Si-MOSFETs
• 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words(Integrated Electronics)
• Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor(Image Processing and Video Processing)
• Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
• Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization
• Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors
• Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation
• An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis
• Interface Magnetism in Fe/Mn Artificial Metallic Superlattice Investigated by ^Mn NMR
• Probability Distribution of Threshold Voltage Fluctuations in Metal-OXide-Semiconductor Field-Effect-Transistors : Semiconductors
• Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories(VLSI Design Technology and CAD)
• A Self-Consistent Non-Quasi-Static MOSFET Model for Circuit Simulation Based on Transient Carrier Response
• High-Electric-Field Electron Transport at Silicon/Silicon-Dioxide Interface Inversion Layer
• Circuit-Simulation Model of C_ Changes in Small-Size MOSFETs Due to High Channel-Field Gradients(the IEEE International Conference on SISPAD '02)
• Coherent Interface Structures Observed in Co/Au(001) Epitaxial Superlattices
• X-Ray Diffraction Measurements of Lattice Strains in Co/Pd(001) Superlattice Filrms
• Ferromagnetic Resonance of Mn/Sb Multilayered Films with Artificial Superstructure
• Monolayer of Ferromagnetic MnSb
• A Structural Study of Co-Sb Multilayered Film by X-Ray Diffraction
• Z_2 Vortex-Induced Broadening of the EPR Linewidth in the Two-Dimensional Triangular Lattice Antiferromagnets,HCrO_2 and LiCrO_2
• Structural Aspects of Fe-Mg Artificial Superstruture Films Studied by X-Ray Diffraction
• A Compact Model of the Pinch-off Region of 100nm MOSFETs Based on the Surface-Potential(Semiconductor Materials and Devices)
• 1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation(Semiconductor Materials and Devices)
• Quantum Effect in Sub-0.1μm MOSFET with Pocket Technologies and Its Relevance for the On-Current Condition
• Circuit Simulation Models for Coming MOSFET Generations(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
• Shot noise modeling in metal-oxide-semiconductor field effect transistors under sub-threshold Condition
• Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
• Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory(Image Processing and Video Processing)
• Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing)
• A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(Novel Device Architectures and System Integration Technologies)
• A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features(Integrated Electronics)
• Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
• Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation(Image Processing and Video Processing)
• Digital Low-Power Real-Time Video Segmentation by Region Growing
• 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions(Devices and Circuits for Next Generation Multi-Media Communication Systems)
• Carrier Transport Model for Lateral p-i-n Photodiode in High-Frequency Operation
• A 2V, 500MHz and 3V, 920MHz Low-Power Current-Mode 0.6μm CMOS VCO Circuit (Special Issue on Microwave and Millimeter Wave Technology)
• Analysis of Within-Die Complementary Metal--Oxide--Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM
• Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
• MOSFET Harmonic Distortion up to the Cutoff Frequency : Measurement and Theoretical Analysis
• 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions
• A Bulk-Current Model for Advanced MOSFET Technologies Without Binning : Substrate Current and Fowler-Nordheim Current
• A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2
• Fast and Compact Central Arbiter for High Access-Bit-Rate Multi-Port Caches
• A PN Junction-Current Model for Advanced MOSFET Technologies
• Bank-Type Associative Memory for High-Speed Nearest Manhattan Distance Search in Large Reference-Pattern Space
• Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation(Image Processing, Image Pattern Recognition)
• Advanced Process/Device Modeling and Its Ompact on the CMOS Design Solution (Special lssue on SISPAD'99)
• Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100nm SOC Circuit Design
• ENERGY ANALYSIS OF ELECTRONS DETACHED FROM CARBON CLUSTER ANIONS INDUCED BY A SURFACE COLLISION
• High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme (Special Issue : Solid State Devices and Materials (2))
• Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture
• Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems
• A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching
• Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal--Oxide--Semiconductor Technology Including Its Distance Dependences
• Compact Modeling of Expansion Effects in LDMOS
• A Self-Consistent Non-Quasi-Static MOSFET Model for Circuit Simulation Based on Transient Carrier Response
• Surface-Potential-Based Metal–Oxide–Silicon-Varactor Model for RF Applications
• Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization
• Mixed Digital–Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search
• Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept
• Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation
• High-Electric-Field Electron Transport at Silicon/Silicon-Dioxide Interface Inversion Layer
• Compact Modeling of Expansion Effects in LDMOS

もっと見る 閉じる

スポンサーリンク