Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization
スポンサーリンク
概要
- 論文の詳細を見る
A laterally diffused metal oxide semiconductor (LDMOS) device enables the realization of a wide range of application voltages by varying impurity concentration and the length of the lightly doped drain contact region. However, this resistive contact region causes the abnormal characteristics observed in capacitances. Here, the HiSIM-LDMOS model based on a complete surface-potential description is demonstrated, which simulates the features of the LDMOS device consistently. With this model, an optimization scheme for the LDMOS device for requested features is discussed.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2008-04-25
著者
-
Mattausch Hans
Hiroshima Univ. Higashihiroshima‐shi Jpn
-
SADACHIKA Norio
Hiroshima University
-
MIURA-MATTAUSCH Mitiko
Hiroshima University
-
MIYAKE Masataka
Hiroshima University
-
Yokomichi Masahiro
Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan
-
Miura-Mattausch Mitiko
Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan
-
Sadachika Norio
Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan
-
Kajiwara Takahiro
Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan
-
Mattausch Hans
Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan
関連論文
- Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor(Image Processing and Video Processing)
- Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization
- Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors
- Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation
- Circuit-Simulation Model of C_ Changes in Small-Size MOSFETs Due to High Channel-Field Gradients(the IEEE International Conference on SISPAD '02)
- A Compact Model of the Pinch-off Region of 100nm MOSFETs Based on the Surface-Potential(Semiconductor Materials and Devices)
- 1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation(Semiconductor Materials and Devices)
- Quantum Effect in Sub-0.1μm MOSFET with Pocket Technologies and Its Relevance for the On-Current Condition
- Circuit Simulation Models for Coming MOSFET Generations(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
- Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
- Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory(Image Processing and Video Processing)
- Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing)
- A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(Novel Device Architectures and System Integration Technologies)
- A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features(Integrated Electronics)
- Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
- Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation(Image Processing and Video Processing)
- Digital Low-Power Real-Time Video Segmentation by Region Growing
- 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions(Devices and Circuits for Next Generation Multi-Media Communication Systems)
- Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
- MOSFET Harmonic Distortion up to the Cutoff Frequency : Measurement and Theoretical Analysis
- A PN Junction-Current Model for Advanced MOSFET Technologies
- Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100nm SOC Circuit Design
- Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems
- Compact Modeling of Expansion Effects in LDMOS
- Compact Modeling of the p-i-n Diode Reverse Recovery Effect Valid for both Low and High Current-Density Conditions
- Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization
- A GIDL-Current Model for Advanced MOSFET Technologies without Binning
- Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation
- Compact Modeling of the p-i-n Diode Reverse Recovery Effect Valid for both Low and High Current-Density Conditions
- Compact Modeling of Expansion Effects in LDMOS