Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

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概要

• 論文の詳細を見る

• This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.

• （社）電子情報通信学会の論文
• 2008-09-01

著者

• Noda H

  System Core Technology Div. System Solution Business Group Renesas Technology Co.

• Dosaka K

  System Core Technology Div. System Solution Business Group Renesas Technology Co.

• Mattausch Hans

  Hiroshima Univ. Higashihiroshima‐shi Jpn

• Mattausch Hans

  Research Center For Nanodevices And Systems Hiroshima University

• Mattausch Hans

  Hiroshima University

• Saito Kazunori

  System Core Technology Div. System Solution Business Group Renesas Technology Co.

• Dosaka Katsumi

  System Core Technology Div. Renesas Technology Corp.

• Mattausch Hans

  Research Institute For Nanodevice And Bio Systems Hiroshima University

• KOIDE Tetsushi

  Research Center for Nanodevices and Systems, Hiroshima University

• Noda Hideyuki

  System Core Technology Div. System Solution Business Group Renesas Technology Co.

• Koide Tetsushi

  Research Institute For Nanodevice And Bio Systems Hiroshima University

• Koide Tetsushi

  Hiroshima Univ. Higashihiroshima‐shi Jpn

• Koide Tetsushi

  Research Center For Nanodevices And Systems Hiroshima University

• KUMAKI Takeshi

  Research Institute for Nanodevice and Bio Systems, Hiroshima University

• ISHIZAKI Masakatsu

  Research Institute for Nanodevice and Bio Systems, Hiroshima University

• KURODA Yasuto

  Network Memory Design Dept., System Solution Business Unit 4, System Solution Business Group, Renesa

• GYOHTEN Takayuki

  System Core Technology Div. System Solution Business Group, Renesas Technology Co.

• ARIMOTO Kazutami

  System Core Technology Div. System Solution Business Group, Renesas Technology Co.

• Kono Yutaka

  Network Memory Design Dept. System Solution Business Unit 4 System Solution Business Group Renesas T

• Noda H

  Hitachi Ltd. Kokubunji‐shi Jpn

• Gyohten Takayuki

  System Core Technology Div. System Solution Business Group Renesas Technology Co.

• Arimoto Kazutami

  System Core Technology Div. Renesas Technology Corp.

• Ishizaki Masakatsu

  Research Institute For Nanodevice And Bio Systems Hiroshima University

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