Koide Tetsushi | Research Center For Nanodevices And Systems Hiroshima University

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概要

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著作論文

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words(Integrated Electronics)
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor(Image Processing and Video Processing)
Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories(VLSI Design Technology and CAD)
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation(Special Section on VLSI Design and CAD Algorithms)
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory(Image Processing and Video Processing)
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing)
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features(Integrated Electronics)
Digital Low-Power Real-Time Video Segmentation by Region Growing
Analysis of Within-Die Complementary Metal--Oxide--Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM
Bank-Type Associative Memory for High-Speed Nearest Manhattan Distance Search in Large Reference-Pattern Space
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation(Image Processing, Image Pattern Recognition)
High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme (Special Issue : Solid State Devices and Materials (2))
Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture
Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems
A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching
Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal--Oxide--Semiconductor Technology Including Its Distance Dependences
Mixed Digital–Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search
Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept

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