A Performance-Driven Floorplanning Method with Interconnect Performance Estimation(Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.
- 社団法人電子情報通信学会の論文
- 2002-12-01
著者
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KOIDE Tetsushi
Research Center for Nanodevices and Systems, Hiroshima University
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Koide Tetsushi
Research Center For Nanodevices And Systems Hiroshima University
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Yamasaki Shinya
Graduate School Of Engineering Hiroshima University
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NAKAYA Shingo
Graduate School of Engineering, Hiroshima University
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Nakaya Shingo
Graduate School Of Engineering Hiroshima University:(present Address)fujitsu Ltd.
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Wakabayashi Shin'ichi
Graduate School Of Engineering Hiroshima University
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