Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture
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概要
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We report a pixel-block scanning-image-segmentation very large scale integration (VLSI) architecture based on a region-growing approach. The input image is divided into pixel blocks in order to process parts of the image in parallel while the pixel status data of the complete image is stored in embedded memory banks. Using the two techniques of (i) limited scan to the boundary of each grown region and (ii) continued block-internal region growing, we have improved the overall segmentation speed and power consumption in comparison to a previous solution. We evaluated the segmentation performance by MATLAB simulation and with a complete application specific integrated circuit (ASIC) design in the case of a one-dimensional scan. Low power dissipation of 44.7 mW and a segmentation performance of 1,000 fps at 8.6 MHz could be achieved. For a two-dimensional scan the block shape and size can be chosen with increased flexibility, and can be optimized to fulfill many different segmentation-speed, power-consumption, and implementation-area requirements. In particular, the pixel-parallel segmentation-unit area can be drastically reduced to 1/10 by changing the pixel-block size from $80 \times 2$ to $4 \times 4$ pixels, which still enables real-time segmentation performance.
- 2009-04-25
著者
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Mattausch Hans
Research Center For Nanodevices And Systems Hiroshima University
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Koide Tetsushi
Research Center For Nanodevices And Systems Hiroshima University
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Koide Tetsushi
Research Institute for Nanodevice and Bio Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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Okazaki Keita
Research Institute for Nanodevice and Bio Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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Awane Kazutoshi
Research Institute for Nanodevice and Bio Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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Nagaoka Naomi
Research Institute for Nanodevice and Bio Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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Sugahara Tatsuya
Research Institute for Nanodevice and Bio Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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Mattausch Hans
Research Institute for Nanodevice and Bio Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan
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