4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words(Integrated Electronics)
スポンサーリンク
概要
- 論文の詳細を見る
The presented unified data/instruction cache design uses multiple banks and features 4 ports, distributed crossbar, different word-length for data and instruction ports, interleaved cache-line words and synchronous access with hidden precharge. A 20.5KByte storage capacity is integrated in 5-metal-layer CMOS logic technology with 200nm minimum gate length and a 3.4ns access-cycle time is achieved. The access bandwidth corresponds to 10 ports with standard word-length, while the cost in increased Si-area is only 25% in comparison to a 1-port cache.
- 2007-11-01
著者
-
Mattausch Hans
Research Center For Nanodevices And Systems Hiroshima University
-
Koide Tetsushi
Research Center For Nanodevices And Systems Hiroshima University
-
Hironaka Tetsuo
Faculty Of Computer Sciences Hiroshima City University
-
JOHGUCHI Koh
Research Center for Nanodevices and Systems, Hiroshima University
-
Johguchi Koh
Research Center For Nanodevices And Systems Hiroshima University
関連論文
- 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words(Integrated Electronics)
- Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor(Image Processing and Video Processing)
- Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories(VLSI Design Technology and CAD)
- A Performance-Driven Floorplanning Method with Interconnect Performance Estimation(Special Section on VLSI Design and CAD Algorithms)
- Circuit-Simulation Model of C_ Changes in Small-Size MOSFETs Due to High Channel-Field Gradients(the IEEE International Conference on SISPAD '02)
- A Compact Model of the Pinch-off Region of 100nm MOSFETs Based on the Surface-Potential(Semiconductor Materials and Devices)
- 1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation(Semiconductor Materials and Devices)
- Quantum Effect in Sub-0.1μm MOSFET with Pocket Technologies and Its Relevance for the On-Current Condition
- Circuit Simulation Models for Coming MOSFET Generations(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
- Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
- Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory(Image Processing and Video Processing)
- Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing)
- A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features(Integrated Electronics)
- Digital Low-Power Real-Time Video Segmentation by Region Growing
- 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions(Devices and Circuits for Next Generation Multi-Media Communication Systems)
- Analysis of Within-Die Complementary Metal--Oxide--Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM
- MOSFET Harmonic Distortion up to the Cutoff Frequency : Measurement and Theoretical Analysis
- 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions
- Fast and Compact Central Arbiter for High Access-Bit-Rate Multi-Port Caches
- Bank-Type Associative Memory for High-Speed Nearest Manhattan Distance Search in Large Reference-Pattern Space
- Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation(Image Processing, Image Pattern Recognition)
- PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model : Design and Implementation of Its Prototype Processor
- High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme (Special Issue : Solid State Devices and Materials (2))
- Low-Power Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning Architecture
- Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems
- A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching
- Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal--Oxide--Semiconductor Technology Including Its Distance Dependences
- Mixed Digital–Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search
- Automatic Pattern-Learning Architecture Based on Associative Memory and Short/Long Term Storage Concept