An Embedded DRAM Hybrid Macro with Auto Signa Management and Enhanced-on-Chip Tester
スポンサーリンク
概要
- 論文の詳細を見る
This paper describes an Embedded DRAM Hybrid Macro, which supports various memory specifications. The eDRAM module generator with Hybrid Macro provides more than 120,000 eDRAM configurations. This eDRAM includes a new architecture called Auto Signal Management (ASM) architecture, which automatically adjusts the timing of the control signals for various eDRAM configurations, and reduces the design Turn Around Time. An Enhanced-on-chip Tester performs the maximum 512bI/O pass/fail simultaneous judgments and the real time repair analysis. The eDRAM testing time is reduced to about 1/64 of the time required using the conventional technique. A test chip is fabricated using a 0.18 /im 4-inetal embedded DRAM technology, which utilizes the triple-well, dual-T_ox, and Co salicide process technologies. This chip achieves a wide voltage range operation of 1.2V at 100 MHz to 1.8 Vat 200 MHz.
- 社団法人電子情報通信学会の論文
- 2003-04-01
著者
-
YAMAZAKI Akira
Renesas Technology
-
MORIHARA Toshinori
Renesas Technology
-
MOROOKA Yoshikazu
Renesas Technology
-
MORISHITA Fukashi
Renesas Technology Corp.
-
WATANABE Naoya
Renesas Technology Corp.
-
HACHISUKA Atsushi
Renesas Technology Corp.
-
OZAKI Hideyuki
Renesas Technology Corp.
-
TAITO Yasuhiko
Renesas Technology Corporation
-
Ozaki H
Renesas Technology Corp.
-
Dosaka K
System Core Technology Div. System Solution Business Group Renesas Technology Co.
-
帶刀 恭彦
(株)ルネサステクノロジ
-
WATANABE Naoya
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
MORISHITA Fukashi
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
TAITO Ysuhiko
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
YAMAZAKI Akira
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
TANIZAKI Tetsushi
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
DOSAKA Katsumi
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
MOROOKA Yoshikazu
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
IGAUE Futoshi
The author is with Mitsubishi Electric Engineering Co., Ltd.
-
FURUE Katsuya
The authors are with System LSI Division, Mitsubishi Electric Corp.
-
NAGURA Yoshihiro
The authors are with System LSI Division, Mitsubishi Electric Corp.
-
KOMOIKE Tatsunori
The authors are with System LSI Division, Mitsubishi Electric Corp.
-
MORIHARA Toshinori
The authors are with System LSI Division, Mitsubishi Electric Corp.
-
HACHISUKA Atsushi
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
ARIMOTO Kazutami
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
OZAKI Hideyuki
The authors are with ULSI Development Center, Mitsubishi Electric Corp.
-
Ozaki Hideyuki
Ulsi Laboratory Mitsubishi Electric Corporation
-
Koide Tetsushi
Research Institute For Nanodevice And Bio Systems Hiroshima University
-
Koide Tetsushi
Hiroshima Univ. Higashihiroshima‐shi Jpn
-
Yamazaki A
Renesas Technology
-
Igaue Futoshi
The Author Is With Mitsubishi Electric Engineering Co. Ltd.
-
YAMAZAKI AKIRA
Neonatal Care Center, Niigata City General Hospital
-
Arimoto Kazutami
System Core Technology Div. Renesas Technology Corp.
-
Morishita Fukashi
System Core Technology Div. Renesas Technology Corp.
-
Furue Katsuya
The Authors Are With System Lsi Division Mitsubishi Electric Corp.
-
Nagura Yoshihiro
The Authors Are With System Lsi Division Mitsubishi Electric Corp.
-
Tanizaki Tetsushi
The Authors Are With Ulsi Development Center Mitsubishi Electric Corp.
-
Morishita Fukashi
Renesas Technology Corporation
関連論文
- A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
- A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros(Integrated Electronics)
- A Low Power Embedded DRAM Macro for Battery-Operated LSIs(Power Optimization)(VLSI Design and CAD Algorithms)
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor(Image Processing and Video Processing)
- A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
- DC Characteristics of InP HBTs under High-Temperature and Bias Stress
- Ultrahigh-Speed InP/InGaAs DHBTs with Very High Current Density(Heterostructure Microelectronics with TWHM2003)
- An Embedded DRAM Hybrid Macro with Auto Signa Management and Enhanced-on-Chip Tester
- A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
- A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs (Special Issue on Circuit Technologies for Memory and Analog LSIs)
- A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories
- A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
- センス同期式書き込み/読出し方式回路を搭載したSRAM I/F混載DRAMコア(MRAM,不揮発メモリ,メモリ,一般)
- The Superconductivity in the Bi-Sr-Ln-Cu-O System (Ln=Pr, Nd and La) : Electrical Properties of Condensed Matter
- A Flexible Search Managing Circuitry for High-Density Dynamic CAMs (Speial Section on High Speed and High Density Multi Functional LSI Memories)
- A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories (Special Issue on LSI Memories)
- Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
- An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's(Special Issue on the 1994 VLSI Circuits Symposium)
- An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
- Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory(Image Processing and Video Processing)
- Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer(Image Processing and Video Processing)
- A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC(Novel Device Architectures and System Integration Technologies)
- A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features(Integrated Electronics)
- Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh(Memory, Low-Power LSI and Low-Power IP)
- Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation(Image Processing and Video Processing)
- Digital Low-Power Real-Time Video Segmentation by Region Growing
- On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform
- A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design(Novel Device Architectures and System Integration Technologies)
- Accomplishment of At-Speed BISR for Embedded DRAMs(Special Issue on Test and Verification of VLSI)
- Total magnetic intensity observed in Iwate volcano
- Factors Affecting Short-Term Mortality in Very Low Birth Weight Infants in Japan
- Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
- A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pluse Width Modulation for AS-Memory
- A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Long Data Retention SOI DRAM with the Body Refresh Function (Special Issue on New Concept Device and Novel Architecture LSIs)
- SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories
- Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems