Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
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概要
- 論文の詳細を見る
This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD)amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.
- 社団法人電子情報通信学会の論文
- 1995-07-25
著者
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OZAKI Hideyuki
Renesas Technology Corp.
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Ozaki H
Renesas Technology Corp.
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MOROOKA Yoshikazu
ULSI Development Center, Mitsubishi Electric Corp.
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OZAKI Hideyuki
ULSI Development Center, Mitsubishi Electric Corp.
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Ozaki Hideyuki
Ulsi Laboratory Mitsubishi Electric Corporation
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FURUTANI Kiyohiro
ULSI Laboratory, Mitsubishi Electric Corporation
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Morooka Yoshikazu
The Ulsi Laboratory Mitsubishi Electric Corporation
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Miyamoto H
Nagoya Inst. Technol. Nagoya‐shi Jpn
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Yamauchi Tadaaki
ULSI Laboratory, Mitsubishi Electric Corporation
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Tanaka Koji
ULSI Laboratory, Mitsubishi Electric Corporation
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Miyamoto Hiroshi
Kita-Itami Works, Mitsubishi Electric Corporation
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Furutani K
Renesas Technol. Corp. Itami‐shi Jpn
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YAMAUCHI Tadaaki
the ULSI Laboratory, Mitsubishi Electric Corporation
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Yamauchi T
Mitsubishi Electric Corp. Itami‐shi Jpn
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Yamauchi Tadaaki
Ulsi Development Center Mitsubishi Electric Corporation
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Tanaka Koji
Ulsi Laboratory Mitsubishi Electric Corporation
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