Morooka Yoshikazu | The Ulsi Laboratory Mitsubishi Electric Corporation

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概要

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著作論文

Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pluse Width Modulation for AS-Memory
Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's

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