MOROOKA Yoshikazu | ULSI Development Center, Mitsubishi Electric Corp.

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著作論文

A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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