Miyamoto H | Nagoya Inst. Technol. Nagoya‐shi Jpn

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著作論文

Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's(Special Issue on the 1994 VLSI Circuits Symposium)
0.15μm CMOS Devices with Reduced Junction Capacitance
An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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