0.15μm CMOS Devices with Reduced Junction Capacitance

概要

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0.15μm CMOS transistors have been fabricated. TiSi_2 salicide was used for the gate electrode and source/drain to reduce parasitic resistance. Electron beam (EB) lithography was used for the gate patterning. Since the channel impurity was implanted only around the gate to reduce the junction capacitance, a reasonably short ring oscillator delay of 33 ps was obtained at 1.9 V supply voltage. The parasitic resistance and capacitance contribution to the delay time was analyzed by SPICE simulation. It was shown that the localized channel implant is effective for scaling the delay time and power consumption, because the source/drain size is difficult to scale down to as small as the gate length.
社団法人電子情報通信学会の論文
1995-03-25