Uniform Si-SEG and Ti/SEG-Si Thickness Ratio Control for Ti-Salicided Sub-Quarter-Micron CMOS Devices
スポンサーリンク
概要
- 論文の詳細を見る
- 1997-09-16
著者
-
TATSUMI Toru
System Devices Research Laboratories, NEC Corporation
-
MOGAMI Tohru
Microelectronics Research Laboratories, NEC Corporation
-
KUNIO Takemitsu
Microelectronics Research Laboratories, NEC Corporation
-
ANDOH Takeshi
ULSI Device Development Research Laboratories, NEC Corporation
-
TATSUMI Toru
Microelectronics Research Laboratories, NEC Corporation
-
Tatsumi Toru
System Devices Research Laboratories Nec Corporation
-
Tatsumi Toru
Microelectronics Research Laboratories Nec Corp.
-
Mogami T
Silicon Systems Research Laboratories Nec Corporation
-
Mogami T
Nec Corp. Sagamihara‐shi Jpn
-
Mogami Tohru
Microelectronics Research Laboratories Nec Corporation
-
Andoh Takeshi
System Lsi Division Nec Corporation
-
Andoh Takeshi
Ulsi Device Development Research Laboratories Nec Corporation
-
KUNIO Takemitsu
Silicon Systems Research Laboratories, NEC Corporation
-
WAKABAYASHI Hitoshi
Silicon Systems Research Laboratories, NEC Corporation
-
Kunio T
Silicon Systems Research Laboratories Nec Corporation
-
WAKABAYASHI Hitoshi
Microelectronics Research Laboratories, NEC Corporation
-
Wakabayashi Hitoshi
Silicon Systems Research Laboratories Nec Corporation
-
Kunio Takemitsu
Microelectronics Research Laboratories Nec
-
Wakabayashi Hitoshi
Silicon Systems Research Labs.
-
Tatsumi Toru
Microelectronics Laboratories Nec Corporation
関連論文
- 1.2nm HfSiON/SiON Stacked Gate Insulators for 65-nm-Node MISFETs
- 1.2nm HfSiON/SiON stacked gate insulators for 65nm-node MISFETs
- Simulated Device Design Optimization to Reduce the Floating Body Effect for Sub-Quarter Micron Fully Depleted SOI-MOSFETs (Special Issue on New Concept Device and Novel Architecture LSIs)
- Quarter-Micron Interconnection Technologies for 256-Mbit Dynamic Random Access Memories
- Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation(High-κ Gate Dielectrics)
- Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation
- A 0.18-μm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO (Special Issue on Low-Power and High-Speed LSI Technologies)
- Effect of Bias Addition on the Gap-Filling Properties of Fluorinated Amorphous Carbon Thin Films Grown by Helicon Wave Plasma-Enhanced Chemical Vapor Deposition
- Characteristics of 0.25 μm Ferroelectric Nonvolatile Memory with a Pb(Zr, Ti)O_3 Capacitor on a Metal/Via-Stacked Plug
- 0.25μm FeRAM with CMVP (Capacitor-on-Metal/Via-Stacked-Plug) Memory Cell
- Multilevel Aluminum Dual-Damascene Interconnects for Process-Step Reduction in 0.18 μm ULSIs
- Multilevel Aluminum Dual-Damascene Interconnects (Al-DDI) for Process-Step Reduction in 0.18um-ULSIs
- Planarized Via-Hole Filling with Molybdenum by Bias Sputtering : Techniques, Instrumentations and Measurement
- 0.15μm CMOS Devices with Reduced Junction Capacitance
- Selective Epitaxial Growth of Si and Si_Ge_x Films by Ultrahigh-Vacuum Chemical Vapor Deposition Using Si_2H_6 and GeH_4
- Temperature Dependence of Etching with Molecular Fluorine on Si(111) Surface
- Suppression of Surface Roughening on Strained Si/SiGe Layers by Lowering Surface Stress
- High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics
- Fully Silicided NiSi Gate Electrodes on HfSiON Gate Dielectrics for Low-Power Applications
- High Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics
- Fully Silicided NiSi Gates on HfSiON Gate Dielectrics for Low Power Application
- TiN as a Phosphorus Outdiffusion Barrier Layer for WSi_x/Doped-Polysilicon Structures (Special Issue on Sub-Half Micron Si Device and Process Technologies)
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
- Uniform Raised-Salicide Technology for High-Performance CMOS Devices(Special Issue on Advanced Sub-0.1μm CMOS Devices)
- Uniform Si-SEG and Ti/SEG-Si Thickness Ratio Control for Ti-Salicided Sub-Quarter-Micron CMOS Devices
- Boron Penetration and Hot-Carrier Effects in Surface-Channel PMOSFETs with p^+ Poly-Si Gates
- Mechanism of Suppressed Change in Effective Work Functions for Impurity-Doped Fully Silicided NiSi Electrodes on Hf-Based Gate Dielectrics
- Analysis of the Origin of the Threshold Voltage Change Induced by Impurity in Fully Silicided NiSi/SiO_2 gate stacks
- Low-Voltage Switching Characteristics of SrBi_2Ta_2O_9 Capacitors
- Ultra-Uniform CMP Using a Hydro Film Buffered Chuck (Hydro Chuck)
- Characterization of Ferroelectric Domain Behavior in MOCVD-PZT Capacitors for CMVP FeRAMs
- Nitrogen Doped Fluorinated Amorphous Carbon Thin Films Grown by Plasma Enhanced Chemical Vapor Deposition
- Hot-Carrier Reliability of 0.1μm Delta-Doped MOSFETs
- High-Resolution Transmission Electron Microscopy of Si/Ge Interfacial Structures
- Effect of Bias Addition on the Gap-Filling Properties of Fluorinated Amorphous Carbon Thin Films Grown by Helicon Wave Plasma Enhanced Chemical Vapor Deposition
- Photoluminescence of Si_Ge_x/Si Quantum Well Structures
- 7-Mask Self-Aligned SiGe Base Bipolar Transistors with f_T of 80 GHz
- Synthesis of PbTiO_3 Thin Films by Surface-Reaction-Enhanced Metal Organic Chemical Vapor Deposition
- Ultrauniform Chemical Mechanical Polishing (CMP) Using a "Hydro Chuck", Featured by Wafer Mounting on a Quartz Glass Plate with Fully Flat, Water-Supported Surface
- SiGe Passivation for Si MBE Regrowth