Simulated Device Design Optimization to Reduce the Floating Body Effect for Sub-Quarter Micron Fully Depleted SOI-MOSFETs (Special Issue on New Concept Device and Novel Architecture LSIs)
スポンサーリンク
概要
- 論文の詳細を見る
Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2 μm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a non-uniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.
- 社団法人電子情報通信学会の論文
- 1997-07-25
著者
-
黄 俐昭
Necシリコンシステム研究所
-
黄 俐昭
Necマイクロエレクトロニクス研究所
-
Kato Haruo
Saitama University
-
KOH Risho
Microelectronics Research Laboratories, NEC Corporation
-
MOGAMI Tohru
Microelectronics Research Laboratories, NEC Corporation
-
KATO Haruo
ULSI Device Development Laboratories, NEC Corporation
-
Mogami Tohru
Microelectronics Research Laboratories Nec Corporation
-
Kato Haruo
Ulsi Device Development Laboratories Nec Corporation
-
Koh R
Silicon Systems Research Labs.
-
Koh Risho
Silicon Systems Research Laboratories Nec Corporation
-
Koh Risho
Microelectronics Reserch Laboratory Nec Corp.
-
Koh Risho
Microelectronics Research Laboratories Nec Corporation
-
Koh Risho
Microelectronics Research Labs. Nec Corp.
-
Koh Risho
Silicon Systems Research Laboratory Nec Corporation
-
Koh Risho
Microelectronics Res. Labs. Nec Corp.
関連論文
- C-11-2 垂直電界に関するバルクMOSFETとSOI-MOSFETの比較
- 素子微細化が真性半導体ボディSOI-MOSFETのI_向上効果に与える影響
- 素子微細化が真性半導体ボディSOI-MOSFETのI_向上効果に与える影響
- 真性チャネルSOI-MOSFETのV_ばらつきに対する電界の二次元効果の影響
- ストライプトゲート真性半導体チャネルSOI-MOSFETのしきい値制御に関するシミュレーション
- X-Ray Detection Using Superconducting Tunnel Junction Shaped Normal-Distribution-Function(Innovative Superconducting Devices and Their Applications)
- Development of Superconducting Tunnel Junctions for the Detection of X-Rays and Heavy Ions(Special Issue on Superconductive Electronics)
- Improved abrication Method for Nb/Al/AIO_x/Al/Nb Superconducting Tunnel Junctions as X-Ray Detectors
- Properties of Substrate Phonon Events in Superconducting Tunnel Junctions Induced by X-Ray Absorption
- X-RAY SPECTROSCOPY OF HIGHLY CHARGED IONS USING SUPERCONDUCTING TUNNEL JUNCTIONS
- Superconducting Tunnel Junctions as General Purpose Detectors
- アクセプタからの電界の二次元的発散を考慮したSOI-MOSFETのしきい値電圧モデル
- 完全空乏化及び部分空乏化型SOI-MOSFETの短チャネル効果に関する容量ネットワークモデルに基づく比較
- SOIMOSFETの基板浮遊効果に及ぼすキャリア消滅の影響についての解析
- Simulated Device Design Optimization to Reduce the Floating Body Effect for Sub-Quarter Micron Fully Depleted SOI-MOSFETs (Special Issue on New Concept Device and Novel Architecture LSIs)
- Planarized Via-Hole Filling with Molybdenum by Bias Sputtering : Techniques, Instrumentations and Measurement
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
- Uniform Si-SEG and Ti/SEG-Si Thickness Ratio Control for Ti-Salicided Sub-Quarter-Micron CMOS Devices
- Boron Penetration and Hot-Carrier Effects in Surface-Channel PMOSFETs with p^+ Poly-Si Gates
- An Investigation on the Short Channel Effect for 0.1 μm Fully Depleted SOIMOSFET Using Equivalent One Dimensional Model
- Capacitance Network Model of the Short Channel Effect for 0.1 μm Fully Depleted SOI MOSFET
- Modeling on the Channel-To-S/D Capacitance and the Short Channel Effect for 0.1μm Fully Depleted SOI-MOSFET
- The Influence of the Device Miniaturization on the I_ Enhancement in the Intrinsic Silicon Body (i-body) SOI-MOSFET's
- A Study of the V_ Fluctuation for 25nm CMOS
- Simulation on A Novel Sub-0.1μm Body Driven SOI-MOSFET (BD-SOIMOS) for Small Logic Swing Operation
- Simulation on a Novel Body-Driven Silicon-on-Insulator Metal-Oxide-Silicon Field-Effect-Transistor for Sub-0.1 μm Small Logic Swing Operation
- Analysis on the Threshold Voltage Fixing and the Floating-Body-Effect Suppression for 0.1μm Fully Depleted SOI-MOSFET
- Analysis of The Threshold Voltage Adjustment and Floating Body Effect Suppression for 0.1 μm Fully Depleted SOI-MOSFET
- Buried Insulator Engineering for sub-0.05μm Fully-Depleted SOI-MOSFET to Reduce the Drain Induced Barrier Lowering
- Simulated Threshold Voltage Adjustment and Drain Current Enhancement in Novel Striped-Gate Nondoped-Channel Fully Depleted SOI-MOSFETs
- Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET