Modeling on the Channel-To-S/D Capacitance and the Short Channel Effect for 0.1μm Fully Depleted SOI-MOSFET
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概要
- 論文の詳細を見る
- 1995-08-21
著者
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黄 俐昭
Necシリコンシステム研究所
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Kato Haruo
Semiconductor Technology Laboratory Research And Development Group Oki Electric Industry Co. Ltd.
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KATO Hiroyo
Semiconductor Technology Laboratory, Research and Development Group, Oki Electric Industry Co. Ltd.
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Kato Hiroyo
Semiconductor Technology Laboratory Research And Development Group Oki Electric Industry Co. Ltd.
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Kato Haruo
Ulsi Device Development Laboratories Nec Corporation
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Koh R
Silicon Systems Research Labs.
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Koh Risho
Microelectronics Res. Labs. Nec Corp.
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MATSUMOTO Hiroshi
Microelectronics Research Laboratories, NEC Corporation
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Matsumoto Hiroshi
Microelectronics Research Laboratories Nec Corporation
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- 素子微細化が真性半導体ボディSOI-MOSFETのI_向上効果に与える影響
- 真性チャネルSOI-MOSFETのV_ばらつきに対する電界の二次元効果の影響
- ストライプトゲート真性半導体チャネルSOI-MOSFETのしきい値制御に関するシミュレーション
- アクセプタからの電界の二次元的発散を考慮したSOI-MOSFETのしきい値電圧モデル
- 完全空乏化及び部分空乏化型SOI-MOSFETの短チャネル効果に関する容量ネットワークモデルに基づく比較
- SOIMOSFETの基板浮遊効果に及ぼすキャリア消滅の影響についての解析
- Simulated Device Design Optimization to Reduce the Floating Body Effect for Sub-Quarter Micron Fully Depleted SOI-MOSFETs (Special Issue on New Concept Device and Novel Architecture LSIs)
- Effects of H_2 Sintering and Pt Upper Electrode on Metallic Bi Content in Sr_Bi_Ta_2O_9 Thin Films for Ferroelectric Memories Prepared by Sol-Gel Method
- Low Voltage Operation of Ferroelectric Sr_Bi_Ta_2O_9 Thin Films Crystallized by Excimer Laser Annealing
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
- ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
- An Investigation on the Short Channel Effect for 0.1 μm Fully Depleted SOIMOSFET Using Equivalent One Dimensional Model
- Capacitance Network Model of the Short Channel Effect for 0.1 μm Fully Depleted SOI MOSFET
- Modeling on the Channel-To-S/D Capacitance and the Short Channel Effect for 0.1μm Fully Depleted SOI-MOSFET
- The Influence of the Device Miniaturization on the I_ Enhancement in the Intrinsic Silicon Body (i-body) SOI-MOSFET's
- A Study of the V_ Fluctuation for 25nm CMOS
- Simulation on A Novel Sub-0.1μm Body Driven SOI-MOSFET (BD-SOIMOS) for Small Logic Swing Operation
- Simulation on a Novel Body-Driven Silicon-on-Insulator Metal-Oxide-Silicon Field-Effect-Transistor for Sub-0.1 μm Small Logic Swing Operation
- Analysis on the Threshold Voltage Fixing and the Floating-Body-Effect Suppression for 0.1μm Fully Depleted SOI-MOSFET
- Analysis of The Threshold Voltage Adjustment and Floating Body Effect Suppression for 0.1 μm Fully Depleted SOI-MOSFET
- Buried Insulator Engineering for sub-0.05μm Fully-Depleted SOI-MOSFET to Reduce the Drain Induced Barrier Lowering
- Defect-Free Reactive Ion Etching of Silicon by SiF_4/Cl_2 Plasma
- Simulated Threshold Voltage Adjustment and Drain Current Enhancement in Novel Striped-Gate Nondoped-Channel Fully Depleted SOI-MOSFETs
- Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET
- Simulation of Chemical Amplification Resists
- Effects of H2 Sintering and Pt Upper Electrode on Metallic Bi Content in Sr0.9Bi2.1Ta2O9 Thin Films for Ferroelectric Memories Prepared by Sol-Gel Method