Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET

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概要

• 論文の詳細を見る

• The influence of the buried layer structure on the drain-induced barrier lowering (DIBL) is investigated for a silicon-on-insulator metal-oxide-silicon field-effect-transistor (SOI-MOSFET) by a two-dimensional device simulator. The buffed layer thickness and the dielectric constant of the buried layer are varied systematically. It is found that the degradation on the threshold voltage can be separated into two components. One component originates from the electric flux via the SOI layer and the other via the buried layer. The buried insulator engineering which controls the thickness and the dielectric constant of the buried layer is effective in reducing the latter component. The gate length limit can be reduced by 23% by the buried air gap structure where the dielectric constant of the buried layer is 1.0.

• 社団法人応用物理学会の論文
• 1999-04-30

著者

• 黄 俐昭

  Necシリコンシステム研究所

• 黄 俐昭

  Necマイクロエレクトロニクス研究所

• Koh R

  Silicon Systems Research Labs.

• Koh Risho

  Silicon Systems Research Laboratories Nec Corporation

• Koh Risho

  Microelectronics Reserch Laboratory Nec Corp.

• Koh Risho

  Microelectronics Research Laboratories Nec Corporation

• Koh Risho

  Microelectronics Research Labs. Nec Corp.

• Koh Risho

  Silicon Systems Research Laboratory Nec Corporation

• Koh Risho

  Microelectronics Res. Labs. Nec Corp.

関連論文

• C-11-2 垂直電界に関するバルクMOSFETとSOI-MOSFETの比較
• 素子微細化が真性半導体ボディSOI-MOSFETのI_向上効果に与える影響
• 素子微細化が真性半導体ボディSOI-MOSFETのI_向上効果に与える影響
• 真性チャネルSOI-MOSFETのV_ばらつきに対する電界の二次元効果の影響
• ストライプトゲート真性半導体チャネルSOI-MOSFETのしきい値制御に関するシミュレーション
• アクセプタからの電界の二次元的発散を考慮したSOI-MOSFETのしきい値電圧モデル
• 完全空乏化及び部分空乏化型SOI-MOSFETの短チャネル効果に関する容量ネットワークモデルに基づく比較
• SOIMOSFETの基板浮遊効果に及ぼすキャリア消滅の影響についての解析
• Simulated Device Design Optimization to Reduce the Floating Body Effect for Sub-Quarter Micron Fully Depleted SOI-MOSFETs (Special Issue on New Concept Device and Novel Architecture LSIs)
• ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
• ELFIN (ELevated Field INsulator) and SEP (S/D Elevated by Poly-Si Plugging) Process for Ultra-Thin SOI MOSFETs
• An Investigation on the Short Channel Effect for 0.1 μm Fully Depleted SOIMOSFET Using Equivalent One Dimensional Model
• Capacitance Network Model of the Short Channel Effect for 0.1 μm Fully Depleted SOI MOSFET
• Modeling on the Channel-To-S/D Capacitance and the Short Channel Effect for 0.1μm Fully Depleted SOI-MOSFET
• The Influence of the Device Miniaturization on the I_ Enhancement in the Intrinsic Silicon Body (i-body) SOI-MOSFET's
• A Study of the V_ Fluctuation for 25nm CMOS
• Simulation on A Novel Sub-0.1μm Body Driven SOI-MOSFET (BD-SOIMOS) for Small Logic Swing Operation
• Simulation on a Novel Body-Driven Silicon-on-Insulator Metal-Oxide-Silicon Field-Effect-Transistor for Sub-0.1 μm Small Logic Swing Operation
• Analysis on the Threshold Voltage Fixing and the Floating-Body-Effect Suppression for 0.1μm Fully Depleted SOI-MOSFET
• Analysis of The Threshold Voltage Adjustment and Floating Body Effect Suppression for 0.1 μm Fully Depleted SOI-MOSFET
• Buried Insulator Engineering for sub-0.05μm Fully-Depleted SOI-MOSFET to Reduce the Drain Induced Barrier Lowering
• Simulated Threshold Voltage Adjustment and Drain Current Enhancement in Novel Striped-Gate Nondoped-Channel Fully Depleted SOI-MOSFETs
• Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET

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