TATSUMI Toru | System Devices Research Laboratories, NEC Corporation

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著作論文

1.2nm HfSiON/SiON Stacked Gate Insulators for 65-nm-Node MISFETs
1.2nm HfSiON/SiON stacked gate insulators for 65nm-node MISFETs
Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation(High-κ Gate Dielectrics)
Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation
High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics
Fully Silicided NiSi Gate Electrodes on HfSiON Gate Dielectrics for Low-Power Applications
High Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics
Fully Silicided NiSi Gates on HfSiON Gate Dielectrics for Low Power Application
Uniform Raised-Salicide Technology for High-Performance CMOS Devices(Special Issue on Advanced Sub-0.1μm CMOS Devices)
Uniform Si-SEG and Ti/SEG-Si Thickness Ratio Control for Ti-Salicided Sub-Quarter-Micron CMOS Devices
Mechanism of Suppressed Change in Effective Work Functions for Impurity-Doped Fully Silicided NiSi Electrodes on Hf-Based Gate Dielectrics
Analysis of the Origin of the Threshold Voltage Change Induced by Impurity in Fully Silicided NiSi/SiO_2 gate stacks
Characterization of Ferroelectric Domain Behavior in MOCVD-PZT Capacitors for CMVP FeRAMs
7-Mask Self-Aligned SiGe Base Bipolar Transistors with f_T of 80 GHz

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