Fully Silicided NiSi Gate Electrodes on HfSiON Gate Dielectrics for Low-Power Applications

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概要

• 論文の詳細を見る
• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2005-04-30

著者

• MORIOKA Ayuka

  System Devices Research Laboratories, NEC Corporation

• WATANABE Heiji

  System Devices Research Laboratories, NEC Corporation

• TATSUMI Toru

  System Devices Research Laboratories, NEC Corporation

• IKARASHI Taeko

  System Devices Research Laboratories, NEC Corp.

• Yoshihara Takuya

  System Devices Research Laboratories Nec Corporation

• Morioka Ayuka

  System Devices Research Laboratories Nec Corporation

• Watanabe Heiji

  System Devices Research Laboratories Nec Corporation

• TAKAHASHI Kensuke

  System Devices Research Laboratories, NEC Corporation

• MANABE Kenzo

  System Devices Research Laboratories, NEC Corporation

関連論文

• Breakdown Mechanisms and Lifetime Prediction for 90-nm-Node Low-Power HfSiON/SiO_2 CMOSFETs
• Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks
• 1.2nm HfSiON/SiON Stacked Gate Insulators for 65-nm-Node MISFETs
• Breakdown Mechanisms and Lifetime Prediction for 90nm-node Low-power HfSiON/SiO_2 CMOSFETs
• Influences of Traps within HfSiON Bulk on Positive- and Negative-Bias Temperature Instability of HfSiON Gate Stacks
• 1.2nm HfSiON/SiON stacked gate insulators for 65nm-node MISFETs
• Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation(High-κ Gate Dielectrics)
• Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation
• High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics
• Fully Silicided NiSi Gate Electrodes on HfSiON Gate Dielectrics for Low-Power Applications
• High Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics
• Fully Silicided NiSi Gates on HfSiON Gate Dielectrics for Low Power Application
• Uniform Raised-Salicide Technology for High-Performance CMOS Devices(Special Issue on Advanced Sub-0.1μm CMOS Devices)
• Uniform Si-SEG and Ti/SEG-Si Thickness Ratio Control for Ti-Salicided Sub-Quarter-Micron CMOS Devices
• Mechanism of Suppressed Change in Effective Work Functions for Impurity-Doped Fully Silicided NiSi Electrodes on Hf-Based Gate Dielectrics
• Analysis of the Origin of the Threshold Voltage Change Induced by Impurity in Fully Silicided NiSi/SiO_2 gate stacks
• Formation of Nickel Self-Aligned Silicide by Using Cyclic Deposition Method
• Characterization of Ferroelectric Domain Behavior in MOCVD-PZT Capacitors for CMVP FeRAMs
• Formation of Nickel Self-Aligned Silicide by Using Cyclic Deposition Method
• 7-Mask Self-Aligned SiGe Base Bipolar Transistors with f_T of 80 GHz
• 1.2 nm HfSiON/SiON Stacked Gate Insulators for 65-nm-Node MISFETs
• Breakdown Mechanisms and Lifetime Prediction for 90-nm-Node Low-Power HfSiON/SiO2 CMOSFETs
• Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks
• Fully Silicided NiSi Gate Electrodes on HfSiON Gate Dielectrics for Low-Power Applications
• Origin of Flatband Voltage Shift in Poly-Si/Hf-Based High-k Gate Dielectrics and Flatband Voltage Dependence on Gate Stack Structure

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