Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks

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概要

• 論文の詳細を見る
• 2005-04-30

著者

• 寺井 真之

  早稲田大学

• Terai Masayuki

  System Devices Research Laboratories Nec Corp.

• FUJIEDA Shinji

  System Devices Research Laboratories, NEC Corporation

• MORIOKA Ayuka

  System Devices Research Laboratories, NEC Corporation

• KOTSUJI Setsu

  System Devices Research Laboratories, NEC Corporation

• SAITOH Motofumi

  System Devices Research Laboratories, NEC Corporation

• Morioka Ayuka

  System Devices Research Laboratories Nec Corporation

• Fujieda Shinji

  System Devices Research Laboratories Nec Corp.

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• 1.2 nm HfSiON/SiON Stacked Gate Insulators for 65-nm-Node MISFETs
• Breakdown Mechanisms and Lifetime Prediction for 90-nm-Node Low-Power HfSiON/SiO2 CMOSFETs
• Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks
• Fully Silicided NiSi Gate Electrodes on HfSiON Gate Dielectrics for Low-Power Applications

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