KOTSUJI Setsu | System Devices Research Laboratories, NEC Corporation
スポンサーリンク
概要
関連著者
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寺井 真之
早稲田大学
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Terai Masayuki
System Devices Research Laboratories Nec Corp.
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FUJIEDA Shinji
System Devices Research Laboratories, NEC Corporation
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MORIOKA Ayuka
System Devices Research Laboratories, NEC Corporation
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KOTSUJI Setsu
System Devices Research Laboratories, NEC Corporation
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SAITOH Motofumi
System Devices Research Laboratories, NEC Corporation
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Morioka Ayuka
System Devices Research Laboratories Nec Corporation
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Fujieda Shinji
System Devices Research Laboratories Nec Corp.
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寺井 真之
日本電気株式会社デバイスプラットフォーム研究所
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YABE Yuko
System Devices Research Laboratories, NEC Corporation
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IWAMOTO Toshiyuki
System Devices Research Laboratories, NEC Corporation
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OGURA Takashi
System Devices Research Laboratories, NEC Corporation
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SAITO Yukishige
System Devices Research Laboratories, NEC Corporation
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WATANABE Hirohito
System Devices Research Laboratories, NEC Corporation
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Yabe Yuko
System Devices Research Laboratories Nec Corp.
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Kotsuji Setsu
System Devices Research Laboratories Nec Corporation
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Terai Masayuki
Department Of Applied Physics Waseda University
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SAITOH Motofumi
NEC Corporation, Device Platforms Research Laboratories
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Saitoh Motofumi
Nec Corporation Device Platforms Research Laboratories
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Ogura Takashi
Silicon Systems Research Laboratories Nec Corporation
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Ogura Takeshi
Ntt Cyber Space Laboratories
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WATANABE Heiji
System Devices Research Laboratories, NEC Corporation
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Ogura T
Ntt Network Innovation Laboratories
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Watanabe Heiji
System Devices Research Laboratories Nec Corporation
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Iwamoto T
Keio Univ. Fujisawa‐shi Jpn
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Ogura Takashi
System Devices And Fundamental Research Nec Corporation
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Saito Yukishige
System Devices Research Laboratories Nec Corp.
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Watanabe Hirohito
System Devices Research Laboratories Nec Corp.
著作論文
- Breakdown Mechanisms and Lifetime Prediction for 90-nm-Node Low-Power HfSiON/SiO_2 CMOSFETs
- Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks
- Breakdown Mechanisms and Lifetime Prediction for 90nm-node Low-power HfSiON/SiO_2 CMOSFETs
- Influences of Traps within HfSiON Bulk on Positive- and Negative-Bias Temperature Instability of HfSiON Gate Stacks