A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pluse Width Modulation for AS-Memory
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概要
- 論文の詳細を見る
- 1996-07-25
著者
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OZAKI Hideyuki
Renesas Technology Corp.
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Ozaki H
Renesas Technology Corp.
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Ozaki Hideyuki
The Ulsi Laboratory Mitsubishi Electric Corporation
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Ozaki Hideyuki
Ulsi Laboratory Mitsubishi Electric Corporation
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Morooka Yoshikazu
The Ulsi Laboratory Mitsubishi Electric Corporation
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YAMAUCHI Tadaaki
the ULSI Laboratory, Mitsubishi Electric Corporation
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Yamauchi T
Mitsubishi Electric Corp. Itami‐shi Jpn
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- Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
- A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pluse Width Modulation for AS-Memory
- Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's